# US 2021/0241836 A1 · Controlling timing and ramp rate of program-inhibit voltage signal during programming to optimize peak current

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- Number: US 2021/0241836 A1
- Document ID: US20210241836A1
- Status: Published application
- Kind: A1
- Application number: 16/778,821
- Filed: 2020-01-31
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Yu-Chung Lien; Huai-Yuan Tseng; Deepanshu Dutta
- Web page: https://patentgrep.com/patent/US20210241836A1

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- G11C 16/30: Power supply circuits
- G11C 16/32: Timing circuits
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- H10B 43/35: with cell select transistors, e.g. NAND
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

## Claims

### Claim 1

An apparatus, comprising;
a set of memory cells arranged in a set of NAND strings;
a set of bit lines, each bit line connected to a respective NAND string in the set of NAND strings;
sense circuits connected to respective memory cells in the set of memory cells via a respective bit line in the set of bit lines, each sense circuit is configured to pass a voltage signal to the respective bit line in a program loop of a program operation when the respective memory cell is to be inhibited from programming;
a voltage source connected to the sense circuits and configured to output the voltage signal, the voltage signal starts at an initial voltage and increases to a program-inhibit voltage; and
a control circuit connected to the voltage source and the sense circuits, the control circuit is configured to instruct the voltage source to begin to output the voltage signal at a time in the program loop which is based on a position of the program loop among a plurality of program loops in the program operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein:
each sense circuit comprises a respective latch and is configured to update the respective latch to indicate whether the respective memory cell is to be inhibited from programming in a program loop;
the control circuit is configured to instruct the voltage source to begin to output the voltage signal after updating of the respective latches is completed by one subset of the sense circuits and while updating of the respective latches is in progress by another subset of the sense circuits when the program loop is in an initial set of program loops of the plurality of program loops; and
the control circuit is configured to instruct the voltage source to begin to output the voltage signal after updating of the respective latches is completed by each of the sense circuits when the program loop is in an intermediate set of program loops of the plurality of program loops.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is configured to instruct the voltage source to begin to output the voltage signal sooner in a program loop which is in an initial set of program loops of the plurality of program loops than in a program loop which is in an intermediate set of program loops of the plurality of program loops.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is configured to instruct the voltage source to begin to output the voltage signal sooner in a program loop when the program loop is in a final set of program loops of the plurality of program loops than when the program loop is in an intermediate set of program loops of the plurality of program loops.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is configured to instruct the voltage source to output the voltage signal at a relatively high ramp up rate in a program loop when the program loop is in initial and final sets of program loops of the plurality of program loops and at a relatively low ramp up rate when the program loop is in an intermediate set of program loops of the plurality of program loops.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein:
each sense circuit comprises a respective latch and is configured to update the respective latch for a program loop to indicate whether the respective memory cell is to be inhibited from programming; and
each sense circuit is configured to pass the voltage signal to the respective bit line at a specified time if updating of the respective latch is completed at the specified time, and, if the updating of the respective latch has not been completed at the specified time, to pass the voltage signal to the respective bit line when updating of the respective latch is completed after the specified time.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein:
the control circuit is configured to instruct the voltage source to output the voltage signal with a regulated ramp up rate until the voltage signal reaches a transition voltage which is below the program-inhibit voltage, after which the voltage signal increases at an unregulated ramp up rate to the program-inhibit voltage; and
the transition voltage is based on the position of the program loop in the plurality of program loops.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein:
the transition voltage is lower in an initial set of program loops of the plurality of program loops than in an intermediate set of program loops of the plurality of program loops.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein:
the transition voltage is lower in a final set of program loops of the plurality of program loops than in an intermediate set of program loops of the plurality of program loops.

### Claim 10 (depends on 7)

The apparatus of claim 7, wherein:
the regulated ramp up rate is higher in initial and final sets of program loops of the plurality of program loops than in an intermediate set of program loops of the plurality of program loops.

### Claim 11

A method, comprising:
increasing a voltage signal from an initial voltage to a program-inhibit voltage during each program loop of a plurality of program loops of a program operation for memory cells, the memory cells are connected to respective sense circuits via respective bit lines; and
connecting the voltage signal to the respective bit lines at the sense circuits, the increasing of the voltage signal occurs sooner in each program loop of one set of program loops of the plurality of program loops than in each program loop of another set of program loops of the plurality of program loops.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
a transition between the one set of program loops and the another set of program loops occurs at a predetermined program loop in the plurality of program loops.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
a transition between the one set of program loops and the another set of program loops occurs at a program loop in the plurality of program loops in which a program milestone is reached.

### Claim 14 (depends on 11)

The method of claim 11, wherein:
the connecting of the voltage signal to the respective bit lines at each sense circuit comprises configuring a respective selector; and
the connecting of the voltage signal to the respective bit lines occurs before the respective selectors are configured in one or more of the sense circuits in each program loop of the one set of program loops and after the respective selectors are configured in each of the sense circuits in each program loop of the another set of program loops.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
updating a respective latch in each of the sense circuits to indicate the respective memory cell is to be programmed in the program loop, wherein the increasing of the voltage signal occurs before the updating of the respective latches is completed in one or more of the sense circuits in each program loop of the one set of program loops and after the updating of the respective latches is completed in each of the sense circuits in each program loop of the another set of program loops.

### Claim 16

An apparatus, comprising:
a set of memory cells arranged in a set of NAND strings;
a set of bit lines, each bit line connected to a respective NAND string in the set of NAND strings;
a voltage source configured to increase a voltage signal from an initial voltage to a program-inhibit voltage; and
sense circuits connected to respective memory cells in the set of memory cells via a respective bit line in the set of bit lines, each sense circuit comprises means for connecting a program-inhibit voltage signal to the respective bit line during a program loop of a program operation when the respective memory cell is to be inhibited from programming, wherein:
the voltage source is configured to begin to increase the program-inhibit voltage signal at a first time for a program loop when the program loop is in one set of program loops of a plurality of program loops of the program operation, and at a second time for the program loop when the program loop is in another set of program loops of the plurality of program loops, wherein the first time is before the second time.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein:
the one set of program loops is an initial set of program loops of the plurality of program loops; and
the another set of program loops is an intermediate set of program loops of the plurality of program loops.

### Claim 18 (depends on 16)

The apparatus of claim 16, wherein:
the one set of program loops is a final set of program loops of the plurality of program loops; and
the another set of program loops is an intermediate set of program loops of the plurality of program loops.

### Claim 19 (depends on 16)

The apparatus of claim 16, wherein:
each sense circuit comprises a respective latch indicating whether the respective memory cell is to be inhibited from programming;
in each sense circuit, the means for connecting the program-inhibit voltage signal to the respective bit line is responsive to the respective latch; and
one subset of the sense circuits is configured to update the respective latches during the increasing of the program-inhibit voltage signal when the program loop is in the one set of program loops.

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein:
another subset of the sense circuits is configured to complete updating of the respective latches before the increasing of the program-inhibit voltage signal when the program loop is in the one set of program loops.