# US 2021/0241835 A1 · Semiconductor device including page buffer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241835 A1 - Document ID: US20210241835A1 - Status: Published application - Kind: A1 - Application number: 16/932,522 - Filed: 2020-07-17 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sung Lae OH; Dong Hyuk KIM; Tae Sung PARK; Soo Nam JUNG - Web page: https://patentgrep.com/patent/US20210241835A1 ## CPC - G11C 16/24: Bit-line control circuits - G11C 7/106: {Data output latches} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2207/002: Isolation gates, i.e. gates coupling bit lines to the sense amplifier - G11C 2207/005: Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other. ## Claims ### Claim 1 A semiconductor device comprising: a plurality of bit lines, classified into a first group and a second group, that are arranged in a first direction alternating between first group bit lines and second group bit lines; a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines; and a second page buffer circuit coupled to the plurality of connection lines, wherein each of the first group and the second group includes: a plurality of bit-line pairs classified into odd bit lines and even bit lines, wherein the plurality of connection lines includes odd connection lines and even connection lines, and wherein odd connection lines corresponding to the odd bit lines are arranged contiguous to each other in the first direction, and even connection lines corresponding to the even bit lines are arranged contiguous to each other in the first direction. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first page buffer circuit includes: a plurality of odd page buffers in which the odd connection lines are arranged contiguous to each other in the first direction; and a plurality of even page buffers in which the even connection lines are arranged contiguous to each other in the first direction. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein: page buffers that correspond to the first group, from among the plurality of odd page buffers and the plurality of even page buffers, are contiguous to each other in a second direction, and wherein with page buffers that correspond to the second group, from among the plurality of odd page buffers and the plurality of even page buffers, are arranged contiguous to each other in the second direction. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein: the plurality of odd page buffers is included in an array, in which a pattern of odd page buffers is repeatedly arranged in the first direction; and the plurality of even page buffers is included in an array, in which a pattern of even page buffers is repeatedly arranged in the first direction. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, wherein the plurality of odd page buffers receives: a first bit-line test signal for controlling lines corresponding to the first group from among the odd connection lines; and a second bit-line test signal for controlling lines corresponding to the second group from among the odd connection lines. ### Claim 6 (depends on 2) The semiconductor device according to claim 2, wherein the plurality of even page buffers receives: a third bit-line test signal for controlling lines corresponding to the first group from among the even connection lines; and a fourth bit-line test signal for controlling lines corresponding to the second group from among the even connection lines. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the first group or the second group of the first page buffer circuit is matched to the first group or second group of the second page buffer circuit, respectively, and to connection lines of the second page buffer circuit. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second page buffer circuit includes: a plurality of odd page buffers in which the odd connection lines are arranged contiguous to each other in a first direction; and a plurality of even page buffers in which the even connection lines are arranged contiguous to each other in the first direction. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the odd connection lines corresponding to odd bit lines of the first group and odd connection lines corresponding to odd bit lines of the second group are alternately arranged. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein the plurality of odd page buffers receives: a first bit-line discharge signal for controlling connection lines corresponding to the first group from among the odd connection lines; and a second bit-line discharge signal for controlling connection lines corresponding to the second group from among the odd connection lines. ### Claim 11 (depends on 8) The semiconductor device according to claim 8, wherein the even connection lines corresponding to even bit lines of the first group and even connection lines corresponding to even bit lines of the second group are alternately arranged. ### Claim 12 (depends on 8) The semiconductor device according to claim 8, wherein the plurality of even page buffers receives: a third bit-line discharge signal for controlling connection lines, from among the even connection lines, corresponding to the first group; and a fourth bit-line discharge signal for controlling connection lines, from among the even connection lines, corresponding to the second group. ### Claim 13 (depends on 8) The semiconductor device according to claim 8, wherein: the plurality of odd page buffers and the plurality of even page buffers are configured such that page buffers corresponding to the first group are arranged contiguous to each other in a second direction and page buffers corresponding to the second group are arranged contiguous to each other in the second direction. ### Claim 14 (depends on 8) The semiconductor device according to claim 8, wherein: the plurality of odd page buffers is arranged in an array, in which a pattern of odd page buffers is repeatedly arranged in the first direction; and the plurality of even page buffers is arranged in an array, in which a pattern of even page buffers is repeatedly arranged in the first direction. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, further comprising: a control signal generation circuit configured to transmit page buffer control signals to the first page buffer circuit and to the second page buffer circuit. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the second page buffer circuit includes: a first transistor configured to selectively discharge the plurality of connection lines in response to a bit-line discharge signal; and a second transistor configured to transmit data of the plurality of connection lines to page buffers in response to a sensing signal, wherein, if one or more bit lines are selected during a test mode, then the bit-line discharge signal and the sensing signal are deactivated. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein the first page buffer circuit includes: a third transistor configured to transmit a first voltage to one or more bit lines in response to a bit-line test signal; a fourth transistor configured to selectively couple the bit line to a bit-line connection node in response to a bit-line selection signal, wherein, if the bit line is selected during a test mode, the bit-line test signal and the bit-line selection signal are activated. ### Claim 18 A semiconductor device comprising: a plurality of bit lines, classified into a first group and a second group, that are arranged in a first direction alternating between first group bit lines and second group bit lines; and a plurality of page buffers coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, wherein each of the first group and the second group includes: a plurality of bit-line pairs classified into odd bit lines and even bit lines, and wherein the plurality of page buffers includes: a plurality of odd page buffers coupled to odd connection lines of the first group and the second group, and the odd page buffers are arranged contiguous to each other in a first direction; and a plurality of even page buffers coupled to even connection lines of the first group and the second group, and the even page buffers are arranged contiguous to each other in the first direction. ### Claim 19 (depends on 18) The semiconductor device according to claim 18, wherein page buffers of the first group are arranged contiguous to each other in a second direction and page buffers of the second group are arranged contiguous to each other in the second direction. ### Claim 20 (depends on 18) The semiconductor device according to claim 18, wherein the plurality of page buffers is arranged in an array, in which a pattern of page buffers is repeatedly arranged in the first direction.