# US 2021/0241834 A1 · Memory system and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241834 A1 - Document ID: US20210241834A1 - Status: Published application - Kind: A1 - Application number: 17/011,555 - Filed: 2020-09-03 - Published: 2021-08-05 - Earliest claimed: 2020-02-05 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Sang Sik KIM; Dae Sung KIM - Web page: https://patentgrep.com/patent/US20210241834A1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/10: Programming or data input circuits - G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation. ## Claims ### Claim 1 A memory system comprising: a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to: detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation. ### Claim 2 The memory system according to claim I, wherein the table includes read voltage application orders corresponding to the plurality of memory blocks, respectively. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the controller is further configured to exclude the second memory block from the problem occurrence candidate group after performing the read operation. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the controller is further configured to set a flag bit for each memory block within the problem occurrence candidate group to a logic high level. ### Claim 5 (depends on 3) The memory system according to claim 3, wherein the controller excludes the second memory block from the problem occurrence candidate group by setting a flag bit for the second memory block to a logic low level. ### Claim 6 (depends on 1) The memory system according to claim 1, wherein the controller is further configured to control the memory device to perform a read retry operation when the read operation fails, ### Claim 7 (depends on 1) The memory system according to claim 1, wherein the table includes a plurality of read voltage application orders. ### Claim 8 (depends on 7) The memory system according to claim 7, wherein the read operation on the second memory block based on the read voltage application order determined by shifts of threshold voltage distributions due to the problem-causing operation. ### Claim 9 (depends on 5) The memory system according to claim 5, wherein the controller is further configured to control the memory device to perform a read operation according to a default read voltage application order, when a flag bit for a memory block corresponding to a subsequent read command is a logic low level. ### Claim 10 (depends on 1) The memory system according to claim 1, wherein the controller is further configured to output error-corrected data when the read operation succeeds. ### Claim 11 A method for operating a memory system, comprising: performing a problem-causing operation on a first memory block among memory blocks included in a plane, in which multi-bit data is stored in each cell; detecting remaining memory blocks, except the first memory block, in the plane, as being in a problem occurrence candidate group; receiving a read command for a second memory block of the problem occurrence candidate group; searching for a read voltage application order corresponding to the second memory block from a table; and performing a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation. ### Claim 12 (depends on 11) The method according to claim 11, wherein the table includes read voltage application orders corresponding to the memory blocks, respectively. ### Claim 13 (depends on 11) The method according to claim 11, further comprising: excluding the second memory block from the problem occurrence candidate group after the read operation is performed. ### Claim 14 (depends on 11) The method according to claim 11, further comprising setting a flag bit for each memory block within the problem occurrence candidate group to a logic high level. ### Claim 15 (depends on 13) The method according to claim 13, wherein the excluding includes setting a flag bit for the second memory block to a logic low level. ### Claim 16 (depends on 11) The method according to claim 11, further comprising: performing a read retry operation when the read operation fails. ### Claim 17 (depends on 11) The method according to claim 11, wherein the table includes a plurality of read voltage application orders. ### Claim 18 (depends on 17) The method according to claim 17, wherein the read operation on the second memory block based on the searched read voltage application order determined by shifts of threshold voltage distributions due to the problem-causing operation. ### Claim 19 (depends on 15) The method according to claim 15, further comprising: performing a read operation according to a default read voltage application order, when a flag bit for a memory block corresponding to a subsequent read command is a logic low level. ### Claim 20 An operating method of a controller, the operating method comprising: controlling a memory device to perform a program operation or an erase operation on a first block; controlling, in response to a command immediately after the program or erase operation, the memory device to perform a first default read operation on a second block based on a secondary set of read voltages, the second block neighboring the first block; and controlling, in response to a command immediately after a successful read operation set including the first default read operation on the second block, the memory device to perform a second default read operation on the second block based on a primary set of read voltages, wherein the primary and secondary sets have different application orders of the read voltages.