# US 2021/0241830 A1 · Hybrid self-tracking reference circuit for rram cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241830 A1 - Document ID: US20210241830A1 - Status: Published application - Kind: A1 - Application number: 17/106,725 - Filed: 2020-11-30 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Zheng-Jun Lin; Chung-Cheng Chou; Yu-Der Chih; Pei-Ling Tseng - Web page: https://patentgrep.com/patent/US20210241830A1 ## CPC - G11C 13/0064: {Verifying circuits or methods} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs} - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 13/0026: {Bit-line or column circuits} - G11C 13/003: {Cell access} - G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2213/79: Array wherein the access device being a transistor - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation. ## Claims ### Claim 1 A current reference circuit for a resistive random-access memory (RRAM) cell, comprising: a configurable resistor network, wherein the configurable resistor network is configured to emulate a resistive element of the RRAM cell; a replica access path, wherein the replica access path is connected to a first terminal of the configurable resistor network and wherein the replica access path emulates an access path associated with the RRAM cell; a replica selector circuit connected to a second terminal of the configurable resistor network and wherein the replica selector circuit emulates a selector circuit associated with the RRAM cell; a step current generator circuit connected to the configurable resistor network, wherein the step current generator is used to adjust the reference current level provided by the current reference circuit; and wherein the replica access path, the configurable resistor network, the replica selector circuit and the step current generator circuit are configured to track of process, voltage and temperature (PVT) variations. ### Claim 2 (depends on 1) The current reference circuit of claim 1, wherein the replica access path includes one or more transistor devices that match the resistance of logic devices, metal wire resistance and leakage associated with the RRAM cell. ### Claim 3 (depends on 1) The current reference circuit of claim 1, wherein the configurable resistor network is configured to match one of: a low resistance state (LRS), a high resistance state (HRS) and a normal resistance state. ### Claim 4 (depends on 3) The current reference circuit of claim 3, wherein the low resistance state (LRS) is used to represent a logic value of 0 and the high resistance state (HRS) is used to represent a logic value of 1. ### Claim 5 (depends on 3) The current reference circuit of claim 3, wherein the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor connected to a first terminal of a second resistor device; a second terminal of the second resistor device connected to a first terminal of a third resistor device; a second terminal of the third resistor device connected to a first terminal of a step resistor device; a second terminal of the step resistor device connected to the replica selector circuit; ### Claim 6 (depends on 5) The current reference circuit of claim 5, provides a high resistance (RH) that matches the high resistance state (HRS) verify level. ### Claim 7 (depends on 5) The current reference circuit of claim 5, wherein: switching the first terminal of the third resistor device to connect directly to the replica access path provides a low resistance (RL) that matches the low resistance state (LRS) verify level; switching the first terminal of the second resistor device to connect directly to the replica access path provides a middle resistance that matches the normal resistance state; and adjusting the step resistor device provides additional adjustment to a resistance value provided by the configurable resistor network. ### Claim 7 (depends on 3) The current reference circuit of claim 3, wherein the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor device connected to the replica access path; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network connected to the replica access path; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device and the third switch device connected to the first terminal of a step resistor device; and a second terminal of the step resistor device connected to the replica selector circuit; ### Claim 8 (depends on 7) The current reference circuit of claim 7, wherein: disabling the second switch device and the third switch device provides a high resistance (RH) that matches the high resistance state (HRS) verify level; disabling the first switch device and the third switch device provides a middle resistance that matches the normal resistance state; disabling the first switch device and the second switch device provides a low resistance (RL) that matches the low resistance state (LRS) verify level; and adjusting the step resistor device provides additional adjustment to a resistance value provided by the configurable resistor network. ### Claim 9 (depends on 1) The current reference circuit of claim 1, wherein the replica selector circuit is a single NMOS transistor device that tracks the selector circuit associated with the RRAM cell. ### Claim 10 (depends on 1) The current reference circuit of claim 1, wherein the replica selector circuit is an array of transistor devices wherein the array includes one of: four transistor devices or nine transistor devices. ### Claim 11 (depends on 10) The current reference circuit of claim 10, wherein the four transistor devices include two sets of two transistors, wherein the two transistors from each set of two transistors are connected in a parallel configuration and the two sets of two transistors are connected in a series configuration. ### Claim 12 (depends on 1) The current reference circuit of claim 1, the step current generator circuit includes: a current generator circuit; a current mirror circuit connected to the current generator circuit; and a first terminal of a switch device connected to the current mirror circuit and a second terminal of the switch device connected to the configurable resistor network, wherein: upon enabling the switch device, a current generated by the current generator circuit and mirrored by the current mirror circuit is used to adjust the reference current level provided by the current reference circuit. ### Claim 13 A system comprising: a resistive random-access memory (RRAM) device wherein the RRAM device includes: a RRAM cell; a first terminal of an access path connected to a first terminal of the RRAM cell; and a selector circuit connected to a second terminal of the RRAM cell; a current reference circuit, wherein the current reference circuit includes: a configurable resistor network, wherein the configurable resistor network is configured to emulate a resistive element of the RRAM cell; a replica access path, wherein a first terminal of the replica access path is connected to a first terminal of the configurable resistor network and wherein the replica access path emulates the access path associated with the RRAM cell; and a replica selector circuit connected to a second terminal of the configurable resistor network and wherein the replica selector circuit emulates the selector circuit associated with the RRAM cell; and a sense amplifier circuit including two input terminals, wherein a second terminal of the access path is connected to one input terminal of the sense amplifier circuit and a second terminal of the replica access path is connected to another input terminal of the sense amplifier circuit. ### Claim 14 (depends on 13) The current reference circuit from the system of claim 13 further comprising: a step current generator circuit connected to the configurable resistor network, wherein the step current generator is used to adjust a reference current level provided by the current reference circuit. ### Claim 15 (depends on 14) The system of claim 14, wherein the replica access path, the configurable resistor network, the replica selector circuit and the step current generator circuit are configured to track process, voltage and temperature (PVT) variations. ### Claim 16 (depends on 13) The system of claim 13, wherein the sense amplifier senses the variations in current between the RRAM device and the reference current level provided by the current reference circuit to determine a data value stored in the RRAM cell. ### Claim 17 (depends on 13) The system of claim 13 wherein, the configurable resistor network is configured to match one of: a low resistance state (LRS), a high resistance state (HRS) and a normal resistance state. ### Claim 18 (depends on 13) The system of claim 13, wherein the configurable resistor network includes: a first terminal of a first resistor device connected to the replica access path; a second terminal of the first resistor device connected to a first terminal of a first switch device; a first terminal of a second resistor device connected to the replica access path; a second terminal of the second resistor device connected to a first terminal of a second switch device; a first terminal of a third resistor network connected to the replica access path; a second terminal of the third resistor device connected to a first terminal of a third switch device; the second terminals of the first switch device, the second switch device and the third switch device connected to the first terminal of a step resistor device; and a second terminal of the step resistor device connected to the replica selector circuit; ### Claim 19 A method, comprising: selectively connecting one of a first RRAM device or a second RRAM device to a first input of a sense amplifier, wherein the each of the first and second RRAM devices include a RRAM cell; configuring a reference circuit to emulate the selected first or second RRAM device; generating a reference current by the reference circuit that tracks process, voltage and temperature (PVT) variations; selectively connecting the reference circuit to a second input of the sense amplifier; and comparing a current value of the selected first or second RRAM device with reference current by the sense amplifier to read data from the first or second RRAM cell. ### Claim 20 (depends on 18) The method of claim 18, wherein configuring a reference circuit to emulate the selected first or second RRAM device includes: configuring a resistor network to match the resistive element of the RRAM cell; configuring a replica access path to match an access path associated with the RRAM cell; and configuring a replica selector circuit to match a selector circuit associated with the RRAM cell.