# US 2021/0241829 A1 · Variable reference based sensing scheme

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- Number: US 2021/0241829 A1
- Document ID: US20210241829A1
- Status: Published application
- Kind: A1
- Application number: 16/782,321
- Filed: 2020-02-05
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ashraf B. ISLAM
- Web page: https://patentgrep.com/patent/US20210241829A1

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G06F 3/0626: {Reducing size or complexity of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/003: {Cell access}
- G11C 13/0035: {Evaluating degradation, retention or wearout, e.g. by counting writing cycles}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A variable reference based sensing scheme is described. In one example, performance of a memory command to access a crosspoint memory device such as a memory read or memory write command involves a sensing operation. In one example, a memory read operation involves applying a voltage across the memory cell and sensing current through the cell. The current through the memory cell is compared with one of multiple reference currents to determine the state of the memory cell. The reference current is selected based on the voltage applied across the memory for the sensing operation. Different reference currents may be used for different types of operations. For example, different reference currents may be selected for a write sensing operation than for a read sensing operation.

## Claims

### Claim 1

A memory device comprising:
a crosspoint memory array; and
input/output (I/O) circuitry to receive a memory access command to access a memory cell of the crosspoint memory array;
control logic to:
determine a voltage to apply across the memory cell in response to receipt of the memory access command, and
select one of multiple reference currents based on the voltage; and
sense circuitry to:
detect a current through the memory cell in response to the applied voltage, and
determine a state of the memory cell based on the detected current relative to the selected reference current.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the control logic is to:
select the voltage from multiple demarcation voltages, wherein each of the multiple reference currents corresponds to one of the multiple demarcation voltages.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the control logic to select one of the multiple demarcation voltages is to:
select one of the multiple demarcation voltages based on elapsed time.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein the control logic to select one of the multiple reference currents is to:
select a reference current corresponding to the selected demarcation voltage.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein:
each of the multiple reference currents is between expected current distributions at the corresponding demarcation voltage.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein:
the memory access command includes a memory read command.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein:
the memory access command includes a memory write command, wherein performance of the memory write command includes: application of one or more voltages across the crosspoint memory cell and detection of the current through the memory cell.

### Claim 8

A system comprising:
a memory controller; and
a memory die in a same package as the memory controller, the memory die comprising:
a crosspoint memory array; and
input/output (I/O) circuitry to receive a memory access command from the memory controller to access a memory cell of the crosspoint memory array;
control logic to:
determine a voltage to apply across the memory cell in response to receipt of the memory access command, and
select one of multiple reference currents based on the voltage; and
sense circuitry to:
detect a current through the memory cell in response to the applied voltage, and
determine a state of the memory cell based on the detected current relative to the selected reference current.

### Claim 9 (depends on 8)

The system of claim 8, wherein the control logic is to:
select the voltage from multiple demarcation voltages, wherein each of the multiple reference currents corresponds to one of the multiple demarcation voltages.

### Claim 10 (depends on 9)

The system of claim 9, wherein the control logic to select one of the multiple demarcation voltages is to:
select one of the multiple demarcation voltages based on elapsed time.

### Claim 11 (depends on 9)

The system of claim 9, wherein the control logic to select one of the multiple reference currents is to:
select a reference current corresponding to the selected demarcation voltage.

### Claim 12 (depends on 11)

The system of claim 11, wherein:
each of the multiple reference currents is between expected current distributions at the corresponding demarcation voltage.

### Claim 13 (depends on 8)

The system of claim 8, wherein:
the memory access command includes a memory read command.

### Claim 14 (depends on 8)

The system of claim 8, wherein:
the memory access command includes a memory write command, wherein performance of the memory write command includes: application of one or more voltages across the crosspoint memory cell and detection of the current through the memory cell.

### Claim 15 (depends on 8)

The system of claim 8, further comprising:
one or more of: a processor, a host memory controller, and a power source.

### Claim 16

A method comprising:
receiving a memory access command to access a crosspoint memory cell;
applying a voltage across the crosspoint memory cell in response to receipt of the memory access command;
selecting one of multiple reference currents based on the voltage;
detecting a current through the memory cell in response to the applied voltage; and
determining a state of the memory cell based on the detected current relative to the selected reference current.

### Claim 17 (depends on 16)

The method of claim 16, wherein:
the voltage is selected from multiple demarcation voltages; and
each of the multiple reference currents corresponds to one of the multiple demarcation voltages.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
selecting one of the multiple demarcation voltages based on elapsed time; and
wherein selecting one of the multiple reference currents comprises: selecting a reference current corresponding to the selected demarcation voltage.

### Claim 19 (depends on 16)

The method of claim 16, wherein:
each of the multiple reference currents is between expected current distributions at the corresponding demarcation voltage.

### Claim 20 (depends on 16)

The method of claim 16, wherein:
the memory access command includes a memory read command.