# US 2021/0241827 A1 · Memory sub-system grading and allocation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241827 A1 - Document ID: US20210241827A1 - Status: Published application - Kind: A1 - Application number: 17/240,014 - Filed: 2021-04-26 - Published: 2021-08-05 - Earliest claimed: 2019-08-27 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Andrew M. Kowles; Kevin R. Brandt - Web page: https://patentgrep.com/patent/US20210241827A1 ## CPC - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G06F 11/102: {Error in check bits} - G11C 7/02: with means for avoiding parasitic signals - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/50: Marginal testing, e.g. race, voltage or current testing - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus includes a component coupleable to a memory device. The component can be configured to analyze a plurality of sets of memory cells of the memory device to determine quality attributes associated with the plurality of sets of memory cells and assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes. The component can be configured to allocate at least one of the plurality of sets of memory cells for use by the memory device based, at least in part, on the assigned grade associated with the one or more sets of the memory cells. ## Claims ### Claim 1 An apparatus, comprising: a processor couplable to a memory device, wherein the processor is to: determine quality attributes associated with a plurality of sets of memory cells of the memory device; assign grades to one or more sets of the memory cells based, at least in part, on the determined quality attributes; and allocate a first one of the plurality of sets of memory cells for data to be retained for greater than a threshold period of time based, at least in part, on the assigned grade associated with a first one of the plurality of sets of memory cells being higher than a grade assigned to a second one of the plurality of sets of memory cells. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the processor is further to allocate the second one of the plurality of sets of memory cells for data to be retained for less than the threshold period of time based, at least in part, on the assigned grade associated with the second one of the plurality of sets of memory cells being lower than the assigned grade of the first one of the plurality of sets of memory cells. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the grades are assigned from a quantity of grades comprising at least three grades. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the quality attributes comprise at a typical page programming time or a typical page read time, or both. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the processor is to allocate the first set of memory cells among the plurality of sets of memory cells that has a higher assigned grade than the second set of memory cells among the plurality of sets of memory cells such that the first set of memory cells is used by the memory device prior to the second set of memory cells being used by the memory device. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the processor is to: allocate the first set of memory cells for a first type of data based on the determination based on a determination that the quality attributes of the first set of memory cells are higher than the quality attributes of the second set of memory cells; and allocate the second set of memory cells for a second type of data based on the determination. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the processor is to: allocate the first set of memory cells as triple level or quad level memory cells based on a determination that the quality attributes of the first set of memory cells are higher than the quality attributes of the second set of memory cells; and allocate the second set of memory cells as triple level or single-level memory cells based on the determination. ### Claim 8 A method, comprising: determining quality attributes associated with a first set of memory cells; determining quality attributes associated with a second set of memory cells; assigning a first grade, a second grade, or a third grade to the first set of the memory cells based, at least in part, on the determined quality attributes of the first set of memory cells; assigning a different one of the first grade, the second grade, or the third grade to the second set of the memory cells based, at least in part, on the determined quality attributes of the second set of memory cells; allocating the first set of memory cells for data to be retained for greater than a threshold period of time based, at least in part on the grade assigned to the first set of memory cells being higher than the grade assigned to the second set of memory cells; and allocating the second set of memory cells for data to be retained for less than the threshold period of time based, at least in part, on the different grade assigned to the second set of memory cells being lower than the grade assigned to the first set of memory cells. ### Claim 9 (depends on 8) The method of claim 8, wherein the quality attributes comprise at least one of a residual bit error rate, an erase disturb susceptibility, a data retention error rate, a program disturb susceptibility measure, a read disturb susceptibility measure, a typical page programming time, a typical page read time, or a physical location of the one or more sets of the memory cells, or any combination thereof ### Claim 10 (depends on 8) The method of claim 8, further comprising allocating the set of memory cells such that a first set of the memory cells is used prior to the second set of memory cells being used by the memory device. ### Claim 11 (depends on 8) The method of claim 8, further comprising: determining that the first grade is indicative of the quality attributes of the first set of memory cells being higher than the quality attributes of the second set of memory cells; allocating the first set of memory cells for a first type of data based on the determination; and allocating the second set of memory cells for a second type of data based on the determination. ### Claim 12 (depends on 8) The method of claim 8, further comprising: assigning the first grade to the first set of the memory cells; assigning the second grade or the third grade to the second set of the memory cells; determining that the first grade is indicative of the quality attributes of the first set of memory cells being higher than the quality attributes of the second set of memory cells; and allocating the second set of memory cells to a particular tier of the memory device based on the determination. ### Claim 13 (depends on 8) The method of claim 8, further comprising: assigning the first grade to the first set of the memory cells; assigning the second grade or the third grade to the second set of the memory cells; determining that the first grade is indicative of the quality attributes of the first plurality of sets of memory cells being higher than the quality attributes of the second plurality of sets of memory cells; and allocating particular sets of the memory cells having the first grade assigned thereto or particular sets of the memory cells having the second grade or the third grade assigned thereto, or both, such that the memory device alternates between using the particular sets of the memory cells having the first grade assigned thereto and the particular sets of the memory cells having the second grade or the third grade assigned thereto. ### Claim 14 A system, comprising: a memory device; and a processor coupled to the memory device, wherein the processor is to: determine quality attributes associated with a first set of memory cells; determine quality attributes associated with a second set of memory cells; assign a first grade to the first set of memory cells based, at least in part, on the on the determined quality attributes of the first set of memory cells; assign a second grade to the second set of memory cells based, at least in part, on the determined quality attributes of the second set of memory cells; and allocate the first set of memory cells for data to be retained for greater than a threshold period of time based, at least in part on the first grade being higher than the second grade. ### Claim 15 (depends on 14) The system of claim 14, wherein the processor is to: allocate the first set of memory cells as multi-level memory cells; and allocate the second set of memory cells as single-level memory cells. ### Claim 16 (depends on 14) The system of claim 14, wherein the processor is to allocate the first set of memory cells or the second set of memory cells such that one of the first set of memory cells or the second set of memory cells are accessed prior to the other of the first set of memory cells or the second set of memory cells. ### Claim 17 (depends on 14) The system of claim 14, wherein the processor is to assign the first grade and the second grade from a continuous spectrum of grades. ### Claim 18 (depends on 14) The system of claim 14, wherein the processor is to allocate the second set of memory cells for data to be retained for less than the threshold period of time based, at least in part, on the second grade being lower than the first grade. ### Claim 19 (depends on 14) The system of claim 14, wherein the quality attributes comprise at least one of a residual bit error rate, an erase disturb susceptibility, a data retention error rate, a typical page programming time, a typical page read time, a program disturb susceptibility measure, a read disturb susceptibility measure, a typical page programming time or a typical page read time, or a physical location of the one or more sets of the memory cells, or any combination thereof. ### Claim 20 (depends on 14) The system of claim 14, wherein the processor is to: test the memory cells to determine whether the grade assigned to the second set of memory cells falls below a predetermined grade threshold; and cause the second set of memory cells to be retired from their current assigned usage or reevaluated for a different application based on the determination.