# US 2021/0241825 A1 · Memory device with signal edge sharpener circuitry

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- Number: US 2021/0241825 A1
- Document ID: US20210241825A1
- Status: Published application
- Kind: A1
- Application number: 17/234,160
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2019-10-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Atul Katoch
- Web page: https://patentgrep.com/patent/US20210241825A1

## CPC

- G11C 11/418: Address circuits
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/417: for memory cells of the field-effect type
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A method, comprising:
deactivating a word line based on a received first signal, the word line operably connected to a memory cell;
transmitting a delayed first signal to signal edge sharpener circuitry operably connected to the word line;
based on the delayed first signal, causing, by the signal edge sharpener circuitry, a rising edge of a second signal on the word line to be pulled up; and
initiating a precharge operation on a bit line.

### Claim 22 (depends on 21)

The method of claim 21, further comprising activating the word line when the precharge operation is completed.

### Claim 23 (depends on 21)

The method of claim 21, wherein the first signal is a clock signal and the delayed first signal is a delayed clock signal.

### Claim 24 (depends on 21)

The method of claim 21, wherein the signal edge sharpener circuitry comprises a p-type transistor.

### Claim 25

A memory device, comprising:
a memory cell;
a word line operably connected to the memory cell;
a delay circuit configured to receive a first signal and output a delayed first signal; and
signal edge sharpener circuitry operably connected to the word line and to the delay circuit, the signal edge sharpener circuitry configured to receive the delayed first signal and responsively pull up a rising edge of a second signal on the word line.

### Claim 26 (depends on 25)

The memory device of claim 25, wherein the first signal is a clock signal and the delayed first signal is a delayed clock signal.

### Claim 27 (depends on 25)

The memory device of claim 25, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises a buffer circuit operably connected to a gate of the p-type transistor.

### Claim 28 (depends on 25)

The memory device of claim 25, further comprising a load circuit operably connected to an output of the delay circuit.

### Claim 29 (depends on 28)

The memory device of claim 28, wherein the load circuit comprises a p-type transistor, the gate of the p-type transistor operably connected to the output of the delay circuit.

### Claim 30 (depends on 25)

The memory device of claim 25, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises:
a select circuit operably connected to a gate of the p-type transistor;
a first plurality of buffer circuits connected in series, wherein a first output of the first plurality of buffer circuits is operably connected to a first input of the select circuit; and
a second plurality of buffer circuits connected in series, wherein a second output of the second plurality of buffer circuits is operably connected to a second input of the select circuit and the first output of the first plurality of buffer circuits is operably connected to an input of the second plurality of buffer circuits,
wherein the select circuit is operable to receive a select signal and based on the select signal, output either the first output or the second output.

### Claim 31 (depends on 25)

The memory device of claim 25, further comprising row driver circuitry operably connected to the word line.

### Claim 32 (depends on 31)

The memory device of claim 31, wherein:
the row driver circuitry comprises first row driver circuitry; and
the signal edge sharpener circuitry comprises second row driver circuitry.

### Claim 33 (depends on 25)

The memory device of claim 25, wherein the memory device is a static random access memory device.

### Claim 34

A system, comprising:
a processing device; and
a memory device operably connected to the processing device, the memory device comprising:
a memory cell;
a word line operably connected to the memory cell, wherein a proximate end of the word line is operably connected to row driver circuitry;
a delay circuit configured to receive a first signal and output a delayed first signal;
signal edge sharpener circuitry operably connected between a distal end of the word line and an output of the delay circuit, the signal edge sharpener circuitry configured to receive the delayed first signal and responsively pull up a rising edge of a second signal on the word line; and
a load circuit operably connected to the output of the delay circuit.

### Claim 35 (depends on 34)

The system of claim 34, wherein
the memory cell is included in an array of memory cells in a memory array; and
the memory device further comprises precharge circuitry operably connected between the processing device and the memory array.

### Claim 36 (depends on 34)

The system of claim 34, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises a buffer circuit operably connected to a gate of the p-type transistor.

### Claim 37 (depends on 34)

The system of claim 34, wherein:
the row driver circuitry comprises a NAND gate operably connected to an inverter circuit;
a first input of the NAND gate is configured to receive an address signal and a second input of the NAND gate is configured to receive a clock signal;
an output of NAND gate is operably connected to an input of the inverter; and
an output of the inverter is operably connected to the word line

### Claim 38 (depends on 34)

The system of claim 34, wherein the load circuit comprises a p-type transistor and a gate of the p-type transistor is operably connected to the output of the delay circuit.

### Claim 39 (depends on 34)

The system of claim 34, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises:
a select circuit operably connected to a gate of the p-type transistor;
a first plurality of buffer circuits connected in series, wherein a first output of the first plurality of buffer circuits is operably connected to a first input of the select circuit; and
a second plurality of buffer circuits connected in series, wherein a second output of the second plurality of buffer circuits is operably connected to a second input of the select circuit and the first output of the first plurality of buffer circuits is operably connected to an input of the second plurality of buffer circuits,
wherein the select circuit is operable to receive a select signal and based on the select signal, output either the first output or the second output.

### Claim 40 (depends on 34)

The system of claim 34, further comprising one or more of:
a communication device operably connected to the processing device;
an input device operably connected to the processing device;
an output device operably connected to the processing device; or
a power supply operably connected to the processing device.