# US 2021/0241822 A1 · Memory device having non-uniform refresh

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- Number: US 2021/0241822 A1
- Document ID: US20210241822A1
- Status: Published application
- Kind: A1
- Application number: 16/973,241
- Filed: 2019-05-25
- Published: 2021-08-05
- Earliest claimed: 2018-06-26
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Thomas Vogelsang
- Web page: https://patentgrep.com/patent/US20210241822A1

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/40626: {Temperature related aspects of refresh operations}
- G11C 2211/4061: Calibration or ate or cycle tuning
- G11C 2211/4062: Parity or ECC in refresh operations
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.

## Claims

### Claim 1

An integrated circuit (IC) memory device comprising:
an array of storage cells configured into multiple banks, each bank including multiple segments;
register storage to store per-segment values representing per-segment refresh rates; and
refresh logic to refresh each segment in accordance with the corresponding per-segment value.

### Claim 2 (depends on 1)

The IC memory device of claim 1, wherein the refresh logic refreshes each segment during self-refresh operations.

### Claim 3 (depends on 1)

The IC memory device of claim 1, wherein the array of storage cells comprise dynamic random access memory (DRAM) storage cells.

### Claim 4 (depends on 3)

The IC memory device of claim 3, wherein the register storage receives the per-segment values from a memory controller.

### Claim 5 (depends on 4)

The IC memory device of claim 4, wherein the per-segment refresh rates represent refresh rates with reference to a nominal refresh rate.

### Claim 6 (depends on 1)

The IC memory device of claim 1, further comprising temperature-compensated refresh circuitry to cooperate with the refresh logic to refresh each segment based on temperature.

### Claim 7 (depends on 6)

The IC memory device of claim 6, wherein the per-segment refresh rates represent multiplier values applied to a global temperature-based refresh rate determined by the temperature-compensated refresh circuitry.

### Claim 8

A method of operation in a memory device, the method comprising:
storing data in an array of storage cells including multiple banks, each bank including multiple segments;
receiving per-segment values representing per-segment refresh rates;
loading the per-segment values in register storage; and
refreshing each segment in accordance with the corresponding per-segment value.

### Claim 9 (depends on 8)

The method of claim 8, wherein the refreshing comprises:
refreshing each segment during a self-refresh operation.

### Claim 10 (depends on 8)

The method of claim 8, wherein the refreshing comprises:
refreshing each segment during an auto-refresh operation.

### Claim 11 (depends on 8)

The method of claim 8, wherein the storing data is carried out in accordance with a dynamic random access memory (DRAM) protocol.

### Claim 12 (depends on 8)

The method of claim 8, wherein the receiving per-segment values comprises:
receiving per-segment values from a memory controller.

### Claim 13 (depends on 8)

The method of claim 8, wherein the per-segment refresh rates represent refresh rates with reference to a nominal rate.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
generating temperature-based refresh rates to cooperate with the received per-segment values to refresh each segment based on temperature.

### Claim 15 (depends on 14)

The method of claim 14, wherein the per-segment refresh rates represent multiplier values applied to the temperature-based refresh parameters generated by the temperature-compensated refresh circuitry.

### Claim 16 (depends on 15)

The method of claim 15, wherein loading the per-segment values in register storage comprises:
transferring the per-segment values to the register storage in response to a mode register write (MRW) command.

### Claim 17

An integrated circuit (IC) dynamic random access memory (DRAM) device comprising:
an array of storage cells configured into multiple banks, each bank including at least a first segment and a second segment;
a mode register to store a first value representing a first refresh rate for refreshing the first segment, the mode register to store a second value representing a second refresh rate for refreshing the second segment; and
refresh logic to refresh each segment in accordance with the corresponding per-segment value.

### Claim 18 (depends on 17)

The IC DRAM device of claim 17, wherein:
the first and second values are free to be different from one another.

### Claim 19 (depends on 17)

The IC DRAM device of claim 17, wherein each of the first and second refresh rates represent absolute refresh rates.

### Claim 20 (depends on 17)

The IC DRAM device of claim 17, further comprising:
temperature-compensated refresh circuitry to cooperate with the refresh logic to refresh each segment based on temperature; and
wherein each of the first and second refresh rates represent multiplier values applied to a global temperature-based refresh rate determined by the temperature-compensated refresh circuitry.