# US 2021/0241820 A1 · Computation in-memory architecture for analog-to-digital conversion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241820 A1 - Document ID: US20210241820A1 - Status: Published application - Kind: A1 - Application number: 17/162,842 - Filed: 2021-01-29 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Avishek BISWAS; Mahesh Madhukar MEHENDALE - Web page: https://patentgrep.com/patent/US20210241820A1 ## CPC - G06F 7/52: Multiplying; Dividing (G06F7/483 - G06F7/491, G06F7/544 take precedence) - G11C 11/4094: Bit-line management or control circuits - G06G 7/16: for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/0495: Quantised networks; Sparse networks; Compressed networks - G06N 3/065: Analogue means - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/16: Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - G11C 11/4099: Dummy cell treatment; Reference voltage generators - G11C 11/419: Read-write [R-W] circuits - G11C 11/54: using elements simulating biological cells, e.g. neuron - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication. ## Claims ### Claim 1 A device, comprising: a comparator configured to provide an indication of a difference between: a positive differential voltage (Vp) on a first terminal coupled to a top plate of each of a first group of differential capacitors; and a negative differential voltage (Vn) on a second terminal coupled to a top plate of each of a second group of differential capacitors; and a control circuit coupled to the comparator, the control circuit configured to: receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first group and the second group, and cause a second driver to provide a ground voltage to bottom plates of the other of the first group and the second group; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication. ### Claim 2 (depends on 1) The device of claim 1, wherein: the first terminal is coupled to a top plate of each of a third group of differential capacitors, the third group including a different number of positive differential capacitors than the first group; and the second terminal is coupled to a top plate of each of a fourth group of differential capacitors, the fourth group including a different number of negative differential capacitors than the second group. ### Claim 3 (depends on 2) The device of claim 2, wherein the control circuit is configured to: responsive to the second indication, cause a third driver to provide the reference voltage to bottom plates of one of the third group and the fourth group, and cause a fourth driver to provide the ground voltage to bottom plates of the other of the third group and the fourth group; receive a third indication of a difference between Vp and Vn; and provide the digital value responsive to the first indication, the second indication, and the third indication. ### Claim 4 (depends on 3) The device of claim 3, wherein: the first terminal is coupled to a top plate of each of a fifth group of differential capacitors, the fifth group including a different number of positive differential capacitors than the first and third groups; and the second terminal is coupled to a top plate of each of a sixth group of differential capacitors, the sixth group including a different number of negative differential capacitors than the second and fourth groups. ### Claim 5 (depends on 4) The device of claim 4, wherein the control circuit is configured to: responsive to the third indication, cause a fifth driver to provide the reference voltage to bottom plates of one of the fifth group and the sixth group, and cause a sixth driver to provide the ground voltage to bottom plates of the other of the fifth group and the sixth group; receive a fourth indication of a difference between Vp and Vn; and provide the digital value responsive to the first indication, the second indication, the third indication, and the fourth indication. ### Claim 6 (depends on 2) The device of claim 2, wherein the first, second, third, and fourth groups are binary-weighted groups. ### Claim 7 (depends on 6) The device of claim 6, wherein: a number of positive differential capacitors in the first group is the same as a number of negative differential capacitors in the second binary-weighted group; and a number of positive differential capacitors in the third binary-weighted group is the same as a number of negative differential capacitors in the fourth binary-weighted group. ### Claim 8 (depends on 1) The device of claim 1, wherein: each of the positive differential capacitors is coupled to a different one of a plurality of bit cells in a row of a compute-in-memory (CIM) array; and each of the negative differential capacitors is coupled to one of the bit cells. ### Claim 9 (depends on 1) The device of claim 1, wherein the capacitors are fabricated on a metal layer separate from and above a layer on which the bit cells are fabricated. ### Claim 10 A method, comprising: connecting top plates of a plurality of positive differential capacitors to provide a positive differential voltage (Vp), the plurality of positive differential capacitors including a first group; connecting top plates of a plurality of negative differential capacitors to provide a negative differential voltage (Vn), the plurality of negative differential capacitors including a second group; determining a first difference between Vp and Vn; responsive to the first difference, providing a reference voltage to bottom plates of one of the first group and the second group, and providing a ground voltage to the bottom plates of the other of the first group and the second group; responsive to providing the reference voltage and the ground voltage, determining a second difference between Vp and Vn; and providing a digital value responsive to the first difference and the second difference. ### Claim 11 (depends on 10) The method of claim 10, wherein: the plurality of positive differential capacitors includes a third group, the third group including a different number of positive differential capacitors than the first group; and the plurality of negative differential capacitors includes a fourth group, the fourth group including a different number of negative differential capacitors than the second group. ### Claim 12 (depends on 11) The method of claim 11, comprising: responsive to the second difference, providing the reference voltage to bottom plates of one of the third group and the fourth group, and providing the ground voltage to the bottom plates of the other of the third group and the fourth group; determining a third difference between Vp and Vn; and providing the digital value responsive to the first indication, the second indication, and the third indication. ### Claim 13 (depends on 12) The method of claim 12, wherein: the plurality of positive differential capacitors includes a fifth group, the fifth group including a different number of positive differential capacitors than the first and third groups; and the plurality of negative differential capacitors includes a sixth group, the sixth group including a different number of negative differential capacitors than the second and fourth groups. ### Claim 14 (depends on 13) The method of claim 13, comprising: responsive to the third difference, providing the reference voltage to bottom plates of one of the fifth group and the sixth group, and providing the ground voltage to the bottom plates of the other of the fifth group and the sixth group; determining a fourth difference between Vp and Vn; and providing the digital value responsive to the first indication, the second indication, the third indication, and the fourth indication. ### Claim 15 (depends on 11) The method of claim 11, wherein the first, second, third, and fourth groups are binary-weighted groups. ### Claim 16 (depends on 15) The method of claim 15, wherein: a number of positive differential capacitors in the first group is the same as a number of negative differential capacitors in the second binary-weighted group; and a number of positive differential capacitors in the third binary-weighted group is the same as a number of negative differential capacitors in the fourth binary-weighted group. ### Claim 17 (depends on 10) The method of claim 10, wherein: each of the positive differential capacitors is coupled to a different one of a plurality of bit cells in a row of a compute-in-memory (CIM) array; and each of the negative differential capacitors is coupled to one of the bit cells. ### Claim 18 (depends on 17) The method of claim 17, comprising fabricating the capacitors on a metal layer separate from and above a layer on which the bit cells are fabricated. ### Claim 19 A device, comprising: a first group of differential capacitors, each of the first group of differential capacitors coupled to a different bit cell in a row of a compute-in-memory (CIM) array; a second group of differential capacitors, each of the second group of differential capacitors coupled to one of the bit cells; a comparator having a comparator output, a comparator non-inverting input, and a comparator inverting input, the comparator non-inverting input coupled to a top plate of each of the first group and the comparator inverting input coupled to a top plate of each of the second group; a first driver having a first driver output and a first driver input, the first driver output coupled to bottom plates of the first group; a second driver having a second driver output and a second driver input, the second driver output coupled to bottom plates of the second group; and a control circuit coupled to the comparator output, the first driver input, and the second driver input, the control circuit configured to: provide output signals to the first and second drivers responsive to the comparator output; and provide a digital output responsive to the comparator output and the output signals. ### Claim 20 (depends on 19) The device of claim 19, comprising: a third group of positive differential capacitors, each of the third group of differential capacitors coupled to a different one of the bit cells from the bit cells coupled to the first group of differential capacitors; a fourth group of differential capacitors, each of the fourth group of differential capacitors coupled to a different one of the bit cells from the bit cells coupled to the second group of differential capacitors; a third driver having a third driver output and a third driver input, the third driver output coupled to bottom plates of the third group; and a fourth driver having a fourth driver output and a fourth driver input, the fourth driver output coupled to bottom plates of the fourth group; wherein: the comparator non-inverting input is coupled to a top plate of each of the third group and the comparator inverting input is coupled to a top plate of each of the fourth group; and the control circuit is configured to provide output signals to the third and fourth driver responsive to the comparator output. ### Claim 21 (depends on 19) The device of claim 19, wherein the capacitors are fabricated on a metal layer separate from and above a layer on which the bit cells are fabricated.