# US 2021/0241819 A1 · Dual SLC/QLC Programming and Resource Releasing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241819 A1 - Document ID: US20210241819A1 - Status: Published application - Kind: A1 - Application number: 16/781,885 - Filed: 2020-02-04 - Published: 2021-08-05 - Earliest claimed: 2020-02-04 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Karin INBAR; Shay BENISTY - Web page: https://patentgrep.com/patent/US20210241819A1 ## CPC - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit} - G06F 13/1673: {using buffers} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough. ## Claims ### Claim at position 1 1-7. (canceled) ### Claim 8 A data storage device, comprising: one or more memory devices; and a controller coupled to the one or more memory devices, the controller configured to: determine whether a first buffer release request for a buffer has been received; determine whether a second buffer release request for the buffer has been received; and release the buffer to an available buffer pool of buffers upon determining that the first buffer release request and the second buffer release request for the buffer have both been received. ### Claim 9 (depends on 8) The data storage device of claim 8, wherein the controller is further configured to hold the data in the buffer until the buffer has been released. ### Claim 10 (depends on 8) The data storage device of claim 8, wherein the controller is further configured to not release the buffer if either the first buffer release request or the second buffer release request has not been received. ### Claim 11 (depends on 8) The data storage device of claim 8, wherein the controller is configured to increment a value of FirstFail from 0 to 1 if a first programming has failed. ### Claim 12 (depends on 11) The data storage device of claim 11, wherein the controller is configured to increment a value of SecondFail from 0 to 1 if a second programming has failed. ### Claim 13 (depends on 12) The data storage device of claim 12, wherein the controller is further configured to not release the buffer if either the FirstFail or the SecondFail is equal to 1. ### Claim 14 (depends on 8) The data storage device of claim 8, wherein the controller is further configured to release the buffer to the available buffer pool of buffers only if both the first buffer release request and the second buffer release request have been received. ### Claim 15 A data storage device, comprising: one or more memory devices; means to determine that a buffer has received two release requests, wherein a first release request of the received two release requests corresponds with a single level cell (SLC) memory program of data, and wherein a second release request of the received two release requests corresponds with a multi level cell (MLC) memory program of the same data; and means to foggy write to MLC memory in parallel with writing to SLC memory. ### Claim 16 (depends on 15) The data storage device of claim 15, further comprising means to receive the first release request. ### Claim 17 (depends on 16) The data storage device of claim 16, further comprising means to receive the second release request. ### Claim 18 (depends on 17) The data storage device of claim 17, further comprising means to release the buffer, wherein the means to release the buffer is configured to release the buffer based upon feedback from the means to determine. ### Claim 19 (depends on 15) The data storage device of claim 15, further comprising means to read data from SLC memory and fine write the data read from SLC memory to the MLC memory. ### Claim 20 (depends on 15) The data storage device of claim 15, further comprising means to release a buffer to an available buffer pool. ### Claim 21 A data storage device, comprising: one or more memory devices; and a controller coupled to the one or more memory devices, the controller configured to: receive a first release request for a buffer; receive a second release request for the buffer; and upon receiving both the first release request and the second release request for the buffer, release the buffer to an available buffer pool. ### Claim 22 (depends on 21) The data storage device of claim 21, wherein the buffer stores data being first programmed to SLC memory and second programmed to MLC memory, and wherein the data being first programmed occurs in parallel to the data being second programmed. ### Claim 23 (depends on 21) The data storage device of claim 21, wherein the first release request indicates that either writing data to SLC memory or foggy writing data to MLC memory has completed. ### Claim 24 (depends on 23) The data storage device of claim 23, wherein the second release request indicates that either the writing the data to the SLC memory or the foggy writing the data to the MLC memory has completed, and wherein the second release request is different than the first release request. ### Claim 25 (depends on 21) The data storage device of claim 21, wherein releasing the buffer comprises completing both writing data to SLC memory and foggy writing data to MLC memory. ### Claim 26 (depends on 25) The data storage device of claim 25, wherein fine writing the data to the MLC memory occurs after the foggy writing data to the MLC memory has completed. ### Claim 27 (depends on 26) The data storage device of claim 26, wherein the fine writing comprises: reading the data from the SLC memory; passing the data through a relocation buffer a single time before the fine writing the data to the MLC memory; and fine writing the data to the MLC memory.