# US 2021/0241818 A1 · Volatile memory device and data sensing method thereof

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- Number: US 2021/0241818 A1
- Document ID: US20210241818A1
- Status: Published application
- Kind: A1
- Application number: 17/002,002
- Filed: 2020-08-25
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dongil LEE; Younghun SEO
- Web page: https://patentgrep.com/patent/US20210241818A1

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/565: {using capacitive charge storage elements}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

## Claims

### Claim 1

A volatile memory device comprising:
a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell;
a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and
a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

### Claim 2 (depends on 1)

The volatile memory device of claim 1, wherein the driving voltage supply circuit is further configured to:
precharge the first bit line using a first precharge voltage by supplying the first precharge voltage in a precharge period of a sensing operation on the first memory cell; and
precharge the second bit line using a second precharge voltage by supplying the second precharge voltage in a precharge period of a sensing operation on the second memory cell,
wherein the second precharge voltage is different from the first precharge voltage.

### Claim 3 (depends on 2)

The volatile memory device of claim 2, wherein a difference between the first precharge voltage and the second precharge voltage corresponds to a difference between a capacitance of the first bit line and a capacitance of the second bit line.

### Claim 4 (depends on 1)

The volatile memory device of claim 1, wherein the first sense amplifier comprises:
a first latch configured to sense a least significant bit (LSB) of the 2-bit data stored in the first memory cell, and latch the LSB to a first sensing bit line pair; and
a second latch configured to sense a most significant bit (MSB) of the 2-bit data stored in the first memory cell, and latch the MSB to a second sensing bit line pair, and
wherein the second sense amplifier comprises:
a third latch configured to sense an LSB of the 2-bit data stored in the second memory cell, and latch the LSB to a third sensing bit line pair; and
a fourth latch configured to sense an MSB of the 2-bit data stored in the second memory cell, and latch the MSB to a fourth sensing bit line pair.

### Claim 5 (depends on 4)

The volatile memory device of claim 4, wherein the driving voltage supply circuit is further configured to:
supply a first power supply voltage having a first voltage level to the first sense amplifier to drive a pull-up terminal of the first latch in at least one of an MSB sensing operation period and an LSB sensing operation period of a sensing operation on the first memory cell; and
supply the first power supply voltage having a second voltage level to the second sense amplifier to drive a pull-up terminal of the third latch in at least one of an MSB sensing operation period and an LSB sensing operation period of a sensing operation on the second memory cell.

### Claim 6 (depends on 5)

The volatile memory device of claim 5, wherein a difference between the first voltage level and the second voltage level corresponds to a difference between the length of the first bit line and the length of the second bit line.

### Claim 7 (depends on 4)

The volatile memory device of claim 4, wherein the driving voltage supply circuit is further configured to:
supply a first power supply voltage having a first voltage level to the first sense amplifier to drive a pull-up terminal of the second latch in an MSB sensing operation period of a sensing operation on the first memory cell; and
supply the first power supply voltage having a second voltage level to the second sense amplifier to drive a pull-up terminal of the fourth latch in an MSB sensing operation period of a sensing operation on the second memory cell.

### Claim 8 (depends on 7)

The volatile memory device of claim 7, wherein a difference between the first voltage level and the second voltage level corresponds to a voltage level for compensating for a difference between a sensing characteristic of the first sense amplifier and a sensing characteristic of the second sense amplifier.

### Claim 9 (depends on 4)

The volatile memory device of claim 4, wherein the driving voltage supply circuit is further configured to:
supply a first power supply voltage having a first voltage level to the first sense amplifier to drive a pull-up terminal of the second latch in a restore operation period of a sensing operation on the first memory cell; and
supply the first power supply voltage having a second voltage level to the second sense amplifier to drive a pull-up terminal of the fourth latch in a restore operation period of a sensing operation on the second memory cell.

### Claim 10 (depends on 9)

The volatile memory device of claim 9, wherein the driving voltage supply circuit is further configured to:
supply a first pull-down voltage having a third voltage level to the first sense amplifier to drive a pull-down terminal of the second latch in the restore operation period of the sensing operation on the first memory cell; and
supply the first pull-down voltage having a fourth voltage level to the second sense amplifier to drive a pull-down terminal of the fourth latch in the restore operation period of the sensing operation on the second memory cell.

### Claim 11

A data sensing method of a volatile memory device, the data sensing method comprising:
precharging a first bit line using a first precharge voltage;
sensing first 2-bit data through a first sense amplifier connected to the first bit line, the first 2-bit data being stored in a first memory cell connected between the first bit line and a selected word line;
precharging a second bit line using a second precharge voltage different from the first precharge voltage, the second bit line having a length greater than a length of the first bit line; and
sensing second 2-bit data through a second sense amplifier connected to the second bit line, the second 2-bit data being stored in a second memory cell connected between the second bit line and the selected word line.

### Claim 12 (depends on 11)

The data sensing method of claim 11, wherein a difference between the first precharge voltage and the second precharge voltage corresponds to a level for compensating for a difference between a sensing characteristic of the first sense amplifier and a sensing characteristic of the second sense amplifier.

### Claim 13 (depends on 11)

The data sensing method of claim 11, wherein the sensing the first 2-bit data comprises:
sensing a most significant bit (MSB) of the first 2-bit data using a first latch driven based on a first power supply voltage; and
latching the MSB of the first 2-bit data in a second latch driven based on a second power supply voltage, and
wherein the sensing the second 2-bit data comprises:
sensing an MSB of the second 2-bit data using a third latch driven based on a third power supply voltage; and
latching the MSB of the second 2-bit data in a fourth latch driven based on a fourth power supply voltage.

### Claim 14 (depends on 13)

The data sensing method of claim 13, wherein a voltage level of the first power supply voltage is different from a voltage level of the third power supply voltage, and
wherein a difference between the voltage level of the first power supply voltage and the voltage level of the third power supply voltage corresponds to a difference between a capacitance of the first bit line and a capacitance of the second bit line.

### Claim 15 (depends on 13)

The data sensing method of claim 13, wherein a voltage level of the second power supply voltage is different from a voltage level of the fourth power supply voltage, and
wherein a difference between the voltage level of the second power supply voltage and the voltage level of the fourth power supply voltage corresponds to a difference between the length of the first bit line and the length of the second bit line.

### Claim 16 (depends on 11)

The data sensing method of claim 11, further comprising:
restoring the sensed first 2-bit data in the first memory cell based on a first pull-up driving voltage and a first pull-down driving voltage; and
restoring the sensed second 2-bit data in the second memory cell based on a second pull-up driving voltage and a second pull-down driving voltage,
wherein the first pull-up driving voltage is different from the second pull-up driving voltage, and the first pull-down driving voltage is different from the second pull-down driving voltage.

### Claim 17 (depends on 11)

The data sensing method of claim 11, wherein a difference between the first precharge voltage and the second precharge voltage is determined based on fail cell distribution appearing when a plurality of cell voltages are applied to each of the first sense amplifier and the second sense amplifier.

### Claim 18

A data sensing method of a memory device comprising volatile memory cells storing single-bit data, the data sensing method comprising:
precharging a first bit line with a first precharge voltage in a sensing operation on a first memory cell connected to the first bit line having a first length;
sensing first 1-bit data stored in the first memory cell;
precharging a second bit line with a second precharge voltage in a sensing operation on a second memory cell connected to the second bit line having a second length that is greater than the first length; and
sensing second 1-bit data stored in the second memory cell.

### Claim 19 (depends on 18)

The data sensing method of claim 18, wherein the second precharge voltage has a voltage level higher than a voltage level of the first precharge voltage.

### Claim 20 (depends on 19)

The data sensing method of claim 19, wherein a difference between the first precharge voltage and the second precharge voltage corresponds to a difference between the first length and the second length.

### Claim at position 21

21-24. (canceled)