# US 2021/0241816 A1 · Semiconductor Device Performing Implicit Precharge Operation

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- Number: US 2021/0241816 A1
- Document ID: US20210241816A1
- Status: Published application
- Kind: A1
- Application number: 17/235,761
- Filed: 2021-04-20
- Published: 2021-08-05
- Earliest claimed: 2019-09-19
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Homare Sato
- Web page: https://patentgrep.com/patent/US20210241816A1

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- H10W 90/00: Package configurations
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 2207/2272: Latency related aspects
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein is an apparatus that includes a first semiconductor chip having a latency counter supplied with a first command and configured to generate a second command when a predetermined period is elapsed after the first command is activated; and a second semiconductor chip having an active control circuit configured to activate a state signal in response to the first command when the state signal is in an inactive state, deactivate the state signal in response to the first command when the state signal is in an active state, and activate the state signal in response to the second command generated based on the first command that is activated when the state signal is in the active state.

## Claims

### Claim 1

A method comprising:
activating a first command at a first time, wherein during the first time a state signal is at a first level;
activating, at a second time subsequent to the first time, the first command and a reset signal after the state signal is set at a second level;
changing the state signal to the first level in response to the reset signal;
activating a second command when a predetermined period is elapsed from the second time; and
changing the state signal to the second level in response to the second command.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
latching the reset signal at the second time and providing the reset signal a set signal based on the reset signal; and
changing the state signal to the second level based on the set signal after the predetermined period is elapsed from the second time.

### Claim 3 (depends on 1)

The method of claim 1, wherein at the first time, a first internal signal is at the second level and a second internal signal is at the first level.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
activating a second set signal in response to the first command being activated at the first time and the first internal signal being at the second level and the second internal signal being at the first level; and
setting the state signal at the second level in response to the second set signal being activated.

### Claim 5 (depends on 1)

The method of claim 1, wherein at the second time, a first internal signal is at the first level and a second internal signal is at the second level.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
latching the reset signal at the first time, wherein the reset signal is inactivate at the first time;
activating the second command when the predetermined time is elapsed from the first time; and
producing a set signal based on the reset signal latched at the first time.

### Claim 7 (depends on 6)

The method of claim 6, wherein the set signal is inactivated in response to the reset signal being inactive.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
issuing a power down command after the second command is activated in a power down mode.

### Claim 9

An apparatus comprising:
a first semiconductor chip having a latency counter supplied with a first command and a clock signal and configured to generate a second command when a predetermined period is elapsed after the first command is issued; and
a second semiconductor chip having an active control circuit configured to activate a state signal in response to the second command generated based on the first command that is activated when the state signal is in an active state, wherein the second semiconductor chip is free of the clock signal.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the second semiconductor comprises a memory cell array.

### Claim 11 (depends on 9)

The apparatus of claim 9, further comprising:
TSVs penetrating through at least one of the first and second semiconductor chips.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the active control circuit comprises:
a FIFO circuit configured to latch a reset signal in response to the first command and output the latched reset signal in response to the second command; and
a state circuit configured to determine whether a memory bank is in an active state, the state circuit includes:
an SR latch circuit configured to be set in response to a first set signal or a second set signal and be reset in response to the reset signal or a pre-charge command;
a plurality of gate circuits configured to receive a bank select signal and the state signal and generate a first internal signal and a second internal signal; and
a plurality of clock gate circuits configured to receive the first internal signal and the second internal signal, wherein the plurality of clock gate signals.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the plurality of clock signals comprises a first clock gate circuit and a second clock gate circuit, and wherein the first internal signal configured to pass through the first clock gate circuit is the second set signal and the second internal configured to pass through the second clock gate circuit is the reset signal.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein the FIFO circuit further comprises:
an input pointer circuit configured to update an input point value in response to the first command;
an output pointer circuit configured to update an output point value in response to the second command;
a first plurality of switch circuits configured to receive the input point value from the input pointer circuit;
a second plurality of switch circuits configured to receive the output point value from the output pointer circuit; and
a plurality of latch circuits coupled to the first plurality of switch circuits and the second plurality of switch circuits, respectively.

### Claim 15 (depends on 13)

The apparatus of claim 13, wherein the plurality of latch circuits is configured to latch the reset signal via a conducting one of the first plurality of switch circuits and output the reset signal as a set signal via a conducting one of the second plurality of switch circuit.

### Claim 16 (depends on 12)

The apparatus of claim 12, wherein the latency counter and the FIFO circuit are reset to an initial state when the clock signal is stopped.

### Claim 17 (depends on 9)

The apparatus of claim 9, wherein the latency counter is configured to operate in synchronous with the clock signal.

### Claim 18

An apparatus comprising:
a memory cell array; and
an active control circuit configured to receive an active command and an internal command and generate a state signal,
wherein the active control circuit is further configured to receive the active command at a first time when the state signal is at a first level and change the state signal to a second level,
wherein the active control circuit is further configured to receive the active command at a second time subsequent to the first time when the state signal is at the second level and activate a reset signal and change the state signal to the first level,
wherein the active control circuit is further configured to receive the internal command after a predetermined time period elapses from the first time and keep the state signal at the second level, and
wherein the active control circuit is further configured to receive the internal command after the predetermined time period elapse from the second time and change the state signal to the second level.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the state signal is at a first level when the memory cell array is in an active state and wherein the state signal is at a second level when the memory cell array is in a pre-charge state.

### Claim 20 (depends on 18)

The apparatus of claim 18, wherein the memory cell array comprises a plurality of memory banks, and wherein the active control circuit is allocated to each memory bank of the plurality of memory banks.