# US 2021/0241815 A1 · Electronic device including memory device and training method

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- Number: US 2021/0241815 A1
- Document ID: US20210241815A1
- Status: Published application
- Kind: A1
- Application number: 17/016,554
- Filed: 2020-09-10
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: KYUMIN PARK
- Web page: https://patentgrep.com/patent/US20210241815A1

## CPC

- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 29/56012: {Timing aspects, clock generation, synchronisation}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 2029/5602: {Interface to device under test}
- G11C 2207/2254: Calibration
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.

## Claims

### Claim 1

An electronic device comprising:
a system-on-chip (SoC) that generates a data strobe signal and a data signal; and
a memory device that receives a power supply voltage and exchanges data with the SoC in response to the data strobe signal and the data signal,
wherein the SoC performs write training that measures a magnitude of a delay of the data strobe signal due to variation in a level of the power supply voltage, and that adjusts a delay of the data signal using a result of the write training.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the write training includes:
a first training mode that aligns the data strobe signal and the data signal while the power supply voltage is a normal power supply voltage applied to the memory device; and
a second training mode that aligns the data strobe signal and the data signal while the power supply voltage is a dropped power supply voltage applied to the memory device.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the SoC obtains a difference between a first delay value of the data signal provided as a result of the first training mode, and a second delay value of the data signal provided as a result of the second training mode to detect delay of the data strobe signal due to variation in the level of the power supply voltage.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the SoC adjusts a setup margin of the data signal using the delay of the data strobe signal.

### Claim 5 (depends on 2)

The electronic device of claim 2, wherein the power supply voltage is a “VDD2” voltage defined in a low power double data rate (LPDDR) standard.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein a voltage difference between the normal power supply voltage and the dropped power supply voltage corresponds to “tDQS2DQ_volt” of the LPDDR standard.

### Claim 7 (depends on 1)

The electronic device of claim 1, further comprising:
a power management integrated circuit (PMIC) that varies the level of the power supply voltage under control of the SoC.

### Claim 8 (depends on 1)

The electronic device of claim 1, wherein the SoC includes:
a training module storing code that when executed performs the write training during a booting operation.

### Claim 9

A training method for an electronic device including a system-on-chip (SoC) and a memory device, the method comprising:
providing a data signal and a data strobe signal from the SoC to the memory device;
setting a level of a power supply voltage provided to the memory device to a normal level to generate a normal power supply voltage;
performing a first training mode to align the data signal with the data strobe signal under a condition that the normal power supply voltage is applied to the memory device;
setting the level of the power supply voltage to a dropped level lower than the normal level to generate a dropped power supply voltage;
performing a second training mode to align the data signal and the data strobe signal under a condition that the dropped power supply voltage is applied to the memory device; and
calculating a delay for the data strobe signal due to variation in the level of the power supply voltage using a result of the first training mode and a result of the second training mode.

### Claim 10 (depends on 9)

The method of claim 9, wherein the power supply voltage is a “VDD2” voltage defined in a low power double data rate (LPDDR) standard.

### Claim 11 (depends on 10)

The method of claim 10, wherein a voltage difference between the normal power supply voltage and the dropped power supply voltage corresponds to “tDQS2DQ_volt” of the LPDDR standard.

### Claim 12 (depends on 9)

The method of claim 9, wherein the calculating of the delay for the data strobe signal includes:
calculating a difference between a first delay value for the data signal determined during the first training mode and a second delay value for the data signal determined during the second training mode; and
defining the delay for the data strobe signal as the calculated difference.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
decreasing a setup margin for the data signal by a given step with reference to the delay for the data strobe signal.

### Claim 14 (depends on 13)

The method of claim 13, wherein the given step is smaller than the delay of the data strobe signal.

### Claim 15

An electronic device comprising:
a memory device driven in response to a power supply voltage;
a host configured to transfer a data signal and a data strobe signal to the memory device; and
a power management integrated circuit (PMIC) configured to provide the power supply voltage to the memory device under control of the host,
wherein the host performs software training that measures a delay of the data strobe signal due to variation in the level of the power supply voltage within the memory device.

### Claim 16 (depends on 15)

The electronic device of claim 15, wherein the memory device includes a storage medium configured to store data, and a peripheral circuit configured to control the storage medium, and
the power supply voltage drives the peripheral circuit.

### Claim 17 (depends on 15)

The electronic device of claim 15, wherein the host performs write training that aligns the data signal and the data strobe signal under a first condition that the power supply voltage is a normal power supply voltage, and under a second condition that the power supply voltage is a dropped power supply voltage in order to measure a delay for the data strobe signal.

### Claim 18 (depends on 17)

The electronic device of claim 17, wherein the host calculates a delay difference for an eye shape of the data signal obtained by performing the write training, and allocates the calculated delay difference as the delay for the data strobe signal.

### Claim 19 (depends on 18)

The electronic device of claim 18, wherein the host adjusts a setup margin of the data signal using the delay for the data strobe signal.

### Claim 20 (depends on 15)

The electronic device of claim 15, wherein the memory device is a Dynamic Random Access Memory (DRAM) operating in accordance with a low power double data rate (LPDDR) standard.

### Claim at position 21

21-26. (canceled)