# US 2021/0241811 A1 · Power mode wake-up for memory on different power domains > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241811 A1 - Document ID: US20210241811A1 - Status: Published application - Kind: A1 - Application number: 17/103,294 - Filed: 2020-11-24 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Che-Ju Yeh; Hau-Tai Shieh; Yi-Tzu Chen - Web page: https://patentgrep.com/patent/US20210241811A1 ## CPC - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/417: for memory cells of the field-effect type - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current. ## Claims ### Claim 1 A power control system, comprising: a power supply rail configured to receive a power supply voltage signal; a first header circuit connected to the power supply rail and having a first output terminal configured to provide a first output voltage signal in a first power domain; a second header circuit connected to the power supply rail and having a second output terminal configured to provide a second output voltage signal in a second power domain; and a control switch connected between the first and second header circuits configured to selectively interconnect the first and second output terminals. ### Claim 2 (depends on 1) The power control system of claim 1, wherein the first header circuit includes a first PMOS transistor having source, drain and gate terminals, wherein the gate terminal is configured to receive a first header control signal that is selectively controlled to turn the first header circuit on during a wake-up mode and turn the first header circuit off during a sleep mode. ### Claim 3 (depends on 2) The power control system of claim 2, wherein the drain terminal of the first PMOS transistor is configured to be the first output terminal. ### Claim 4 (depends on 1) The power control system of claim 1, wherein the second header circuit includes a second PMOS transistor having a source, drain and gate terminals, wherein the gate terminal is configured to receive a second header control signal that is selectively controlled to turn the second header circuit on during a wake-up mode and turn the second header circuit off during a sleep mode. ### Claim 5 (depends on 4) The power control system of claim 4, wherein the drain terminal of the second PMOS transistor is configured to be the second output terminal. ### Claim 6 (depends on 1) The power control system of claim 1, wherein the control switch includes a third PMOS transistor having a source, drain and gate terminals, wherein the source terminal is connected to the first output terminal, the drain terminal is connected to the second output terminal and the gate terminal is configured to receive a switch control signal. ### Claim 7 (depends on 6) The power control system of claim 6, wherein the switch control signal is configured to selectively cause the PMOS transistor to: form an electrical connection between the first output signal and the second output signal or break the electrical connection between the first output signal and the second output signal. ### Claim 8 (depends on 1) The power control system of claim 1, wherein the first power domain is configured to supply power to at least a first peripheral circuit and the second power domain is configured to supply power to at least a second peripheral circuit. ### Claim 9 (depends on 8) The power control system of claim 8, wherein the first peripheral circuit and the second peripheral circuit include circuits peripheral to a memory array. ### Claim 10 (depends on 9) The power control system of claim 9, wherein circuits peripheral to the memory array include: word line driver, decoder, and sense amplifier. ### Claim 11 (depends on 9) The power control system of claim 9, wherein the memory array is a SRAM memory array. ### Claim 12 A memory system, comprising: an array of memory cells; a first plurality of peripheral circuits connected to the array of memory cells; a second plurality of peripheral circuits connected to the array of memory cells; a power supply rail configured to receive a power supply voltage signal; a first power control cell including: a first header circuit connected to the power supply rail and having a first output terminal connected to the first plurality of peripheral circuits to provide a first output voltage signal in a first power domain; and a second header circuit connected to the power supply rail and having a second output terminal connected to the second plurality of peripheral circuits to provide a second output voltage signal in a second power domain; a second power control cell including: a third header circuit connected to the power supply rail and having a third output terminal connected to a third plurality of peripheral circuits to provide a third output voltage signal in a third power domain; and the second header circuit connected to the power supply rail and having the second output terminal connected to the second plurality of peripheral circuits to provide the second output voltage signal in a second power domain; a first control switch connected between the first and second header circuits configured to selectively interconnect the first and second output terminals, and a second control switch connected between the second and third header circuits configured to selectively interconnect the second and third output terminals. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the first header circuit includes a PMOS transistor having a source, drain and gate terminals, wherein the gate terminal is configured to receive a first header control signal that is selectively controlled to turn the first header circuit on during a wake-up mode and turn the first header circuit off during a sleep mode. ### Claim 14 (depends on 12) The memory system of claim 12, wherein the second header circuit includes a PMOS transistor having a source, drain and gate terminals, wherein the gate terminal is configured to receive a second header control signal that is selectively controlled to turn the second header circuit on during a wake-up mode and turn the second header circuit off during a sleep mode. ### Claim 15 (depends on 12) The memory system of claim 12, wherein the first control switch includes a PMOS transistor having source, drain and gate terminals, wherein the source terminal is connected to the first output terminal, the drain terminal is connected to the second output terminal and the gate terminal is configured to receive a first switch control signal configured to selectively cause the PMOS transistor to: form an electrical connection between the first output terminal and the second output terminal or break the electrical connection between the first output terminal and the second output terminal. ### Claim 16 (depends on 12) The memory system of claim 12, wherein the second control switch includes a PMOS transistor having source, drain and gate terminals, wherein the source terminal is connected to the second output terminal, the drain terminal is connected to the third output terminal and the gate terminal is configured to receive a second switch control signal configured to selectively cause the PMOS transistor to: form an electrical connection between the second output terminal and the third output terminal or break the electrical connection between the second output terminal and the third output terminal. ### Claim 17 (depends on 12) The memory system of claim 12, wherein the array of memory cells is a SRAM memory array. ### Claim 18 A method, comprising: providing a memory array; providing a first plurality of peripheral circuits connected to the memory array; providing a second plurality of peripheral circuits connected to the memory array; providing a first header circuit having a first output terminal, wherein the first header circuit is connected to a power supply rail and the first output terminal is connected to the first plurality of peripheral circuits; providing a second header circuit having a second output terminal, wherein the second header circuit is connected to the power supply rail and the second output terminal is connected to the second plurality of peripheral circuits; turning off the first header circuit to disconnect the first plurality of peripheral circuits from the power rail in response to a sleep mode command; turning off the second header circuit to disconnect the second plurality of peripheral circuits from the power rail in response to the sleep mode command; turning on the first header circuit to connect the first plurality of peripheral circuits to a first supply voltage in a first power domain in response to a wake-up mode command; and interconnecting the output terminals of the first and second header circuits in response to the wake-up command to supply the first supply voltage to the second plurality of peripheral circuits without turning on the second header circuit. ### Claim 19 (depends on 18) The method of claim 18, wherein the output terminals of the first and second header circuits are interconnected using a PMOS transistor device having a source, drain and gate terminals, wherein the source terminal of the PMOS transistor device is connected to the output terminal of the first header circuit, the drain terminal of the PMOS transistor device is connected to the output terminal of the second header device, and wherein the method further comprises: applying a switch control signal to the gate terminal of the PMOS transistor device. ### Claim 20 (depends on 19) The method of claim 19, wherein the switch control signal is configured to selectively cause the PMOS transistor to form an electrical connection between the output terminal of the first header circuit and the output terminal of the second header circuit or break the electrical connection between the output terminal of the first header circuit and the output terminal of the second header circuit.