# US 2021/0241808 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241808 A1 - Document ID: US20210241808A1 - Status: Published application - Kind: A1 - Application number: 17/158,301 - Filed: 2021-01-26 - Published: 2021-08-05 - Earliest claimed: 2020-02-03 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Shunya NAGATA; Yoshikazu SAITO; Takeshi HASHIZUME - Web page: https://patentgrep.com/patent/US20210241808A1 ## CPC - G11C 8/10: Decoders - G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 29/024: {in decoders} - G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns - G11C 29/54: Arrangements for designing test circuits, e.g. design for test [DFT] tools - G11C 2029/1202: {Word line control} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method. ## Claims ### Claim 1 A semiconductor device comprising: a memory cell array arranged in a matrix; a plurality of word lines provided corresponding to each row of the matrix of the memory cell array; a word driver configured to drive one of the word lines; a plurality of row selecting lines coupled to the word driver; a first row encoder coupled to the word lines and configured to generate a first row address information based on signal levels of the word lines; a second row encoder coupled to the word lines and configured to generate a second row address information which is complementary to the first row address information; and a first row determination circuit configured to output a first row determination signal based on comparation between the first row address information and the second row address information. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a plurality of bit lines provided corresponding to each column of the matrix of the memory cell array a column selecting circuit configured to select one of the bit lines; a plurality of column selecting lines coupled to the column selecting circuit; a column decoder configured to output column selecting signals to the column selecting lines based on input column address information; a first column encoder coupled to the column selecting lines and configured to output a first column address information based on signal levels of the column selecting lines; a first column encoder coupled to the column selecting lines and configured to output a second column address information which is complementary to the first column address information based on signal levels of the column selecting lines; and a first column determination circuit configured to output a first column determination signal based on comparation between the first column address information and the second column address information. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, further comprising: a second row determination circuit configured to output a second row determination signal based on comparation between the input row address information and the first row address information; and a second column determination circuit configured to output a second column determination signal based on comparation between the input row address information and the first column address information. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, further comprising: an output row address information generating circuit configured to generate an output row address information based on the first column determination signal and the first row address information; and an output column address information generating circuit configured to generate an output column address information based on the first row determination signal and the first column address information. ### Claim 5 (depends on 2) The semiconductor device according to claim 2, further comprising: a comparison result determination circuit configured to generate a comparison result signal based on the first row determination signal and the first column determination signal; an output row address information generating circuit configured to generate an output row address information based on the comparison result signal and the first row address information; and an output column address information generating circuit configured to output an output column address information based on the comparison result signal and the first column address information. ### Claim 6 (depends on 4) The semiconductor device according to claim 4 further comprising an address comparison circuit configured to compare an input address information and an output address information, wherein the input address information includes the input row address information and the input column address information, and wherein the output address information includes the output row address information and the output column address information. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, further comprising a first test circuit configured to output a first test pattern signal to the first row encoder and the second row encoder when a test state. ### Claim 8 (depends on 2) The semiconductor device according to claim 2, further comprising a second test circuit configured to output a second test pattern signal to the first column encoder and the second column encoder when a test state. ### Claim 9 A semiconductor device comprising: a memory cell array arranged in a matrix; a plurality of word lines provided corresponding to each row of the matrix of the memory cell array; a word driver configured to drive one of the word lines; a plurality of row selecting lines coupled to the word driver; a row decoder configured to output a row selecting signal to the row selecting lines based on an input row address information; a first data line; a second data line; a plurality of first transistors provided corresponding to each word line and between the first data line and a fixed potential line; a plurality of second transistors provided corresponding to each word line and between the second data line and the fixed potential line; a first current mirror circuit configured to drive the first data line with a first current; a second current mirror circuit configured to drive the second data line with a second current; and a first determination circuit configured to output a first determination signal based on the signal of the first and the second data lines, wherein the first and second transistors are configured to be conductive state according to the signal level of the word lines. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, further comprising: a plurality of bit lines provided corresponding to each column of the matrix of the memory cell array; a column selecting circuit configured to select one of the bit lines; a plurality of column selecting lines coupled to the column selecting circuit; a column decoder configured to output a column selecting signal to the column selecting lines based on an input column address information; a third data line; a fourth data line; a plurality of third transistors provided corresponding to each column selecting line and between the third data line and the fixed potential line; a plurality of fourth transistors provided corresponding to each column selecting line and between the fourth data line and the fixed potential line; a third current mirror circuit configured to drive the third data line with the first current; a fourth current mirror circuit configured to drive the fourth data line with the second current; and a second determination circuit configured to output a second determination signal based on the signal of the third and the fourth data lines, wherein the third and fourth transistors are configured to be conductive state according to the signal level of the column selecting lines. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, further comprising a synthesis circuit configured to output a comparison result based on the first determination signal and the second determination signal. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, further comprising: a dummy word line, a first dummy transistor provided corresponding to the dummy word line and between the first data line and a fixed potential line; and a second dummy transistor provided corresponding to the dummy word line and between the second data line and the fixed potential line, wherein the first and the second dummy transistors configured to be a conductive state based on the signal level of the dummy word line when a test state. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, further comprising: a dummy column selecting line; a third dummy transistor provided corresponding to the dummy column selecting line and between the third data line and the fixed potential line; and a fourth dummy transistor provided corresponding to the dummy column selecting line and between the fourth data line and the fixed potential line, wherein the third and the fourth dummy transistors configured to be a conductive state based on the signal level of the dummy column selecting line when a test state. ### Claim 14 A semiconductor device comprising: a memory cell array arranged in a matrix; a plurality of word lines provided corresponding to each row of the matrix of the memory cell array; a word driver configured to drive one of the word lines; a plurality of row selecting lines coupled to the word driver; a row decoder configured to output a row selecting signal to the row selecting lines based on an input row address information; a first reference voltage generating circuit configured to generate a first reference voltage; a second reference voltage generating circuit configured to generate a second reference voltage; a first data line; a plurality of first transistors provided corresponding to each word line and between the first data line and a fixed potential line; a first sense amplifier configured to output a first comparison signal based on a voltage comparison between the first data line and the first reference voltage; a second sense amplifier configured to output a second comparison signal based on a voltage comparison between the first data line and the second reference voltage; and a first determination circuit configured to output the first determination result based on the first comparison signal and the second comparison signal, wherein the first and second transistors are configured to be conductive state according to the signal level of the word lines. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, further comprising: a plurality of bit lines provided corresponding to each column of the matrix of the memory cell array; a column selecting circuit configured to select one of the bit lines; a plurality of column selecting lines coupled to the column selecting circuit; a column decoder configured to output a column selecting signal to the column selecting lines based on an input column address information; a third reference voltage generating circuit configured to generate a third reference voltage; a fourth reference voltage generating circuit configured to generate a fourth reference voltage; a second data line; a plurality of second transistors provided corresponding to each bit line and between the second data line and the fixed potential line; a third sense amplifier configured to output a third comparison signal based on a voltage comparison between the second data line and the third reference voltage; a fourth sense amplifier configured to output a fourth comparison signal based on a voltage comparison between the second data line and the fourth reference voltage; and a second determination circuit configured to output a second determination signal based on the signal of the third and the fourth comparison signals, wherein the second transistors are configured to be conductive state according to the signal level of the column selecting lines. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, further comprising a synthesis circuit configured to output a determination signal based on the first and the second determination results.