# US 2021/0241803 A1 · Memory device and power management method using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241803 A1 - Document ID: US20210241803A1 - Status: Published application - Kind: A1 - Application number: 17/031,925 - Filed: 2020-09-25 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Sanjeev Kumar Jain - Web page: https://patentgrep.com/patent/US20210241803A1 ## CPC - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 11/417: for memory cells of the field-effect type - G11C 11/418: Address circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device that is operable at a first voltage domain and a second voltage domain includes a memory array, a power saving mode pin and a word line level shifter circuit. The memory array operates at the first voltage domain. The power saving mode pin is configured to receive a power saving mode enable signal that is at the second voltage domain. The power saving mode enable signal is configured to enable a power saving mode of the memory device. The word line level shifter circuit is coupled to the memory array and the power saving mode pin, and is configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device. ## Claims ### Claim 1 A memory device operable at a first voltage domain and a second voltage domain, the memory device comprising: a memory array, configured to operate at the first voltage domain; a power saving mode pin, configured to receive a power saving mode enable signal that is at the second voltage domain, wherein the power saving mode enable signal is configured to enable a power saving mode of the memory device; and a word line level shifter circuit, coupled to the memory array and the power saving mode pin, configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode of the memory device. ### Claim 2 (depends on 1) The memory device of claim 1, wherein voltage levels of the first voltage domain are higher than voltage levels of the second voltage domain, and the predetermined voltage level corresponding to the first state is zero volt. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the power saving mode pin is configured to receive the power saving mode enable signal from outside of the memory device, when the power saving mode enable signal is in the first logic state, the memory device is not in the power saving mode, and when the power saving mode enable signal is in a second logic state, the memory device is in the power saving mode. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the word line level shifter circuit comprises: a first node; a first transistor, coupled to the first node and the power saving mode pin, configured to clamp the first node to the first logic state during the power saving mode based on the power saving mode enable signal; a second node; and a second transistor, coupled to the first node and the second node, configured to clamp the second node to the second logic state during the power saving mode. ### Claim 5 (depends on 4) The memory device of claim 4, wherein the word line level shifter circuit further comprises: a logic circuit, operated at the first voltage domain, having an input terminal coupled to the second node and an output terminal coupled to the word line, and configured to perform a logic operation to clamp the word line to the predetermined voltage level that corresponds to the first logic state during the power saving mode. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the second logic circuit is an inverter circuit that is configured to invert the logic state at the second node to clamp the word line to the predetermined voltage level that corresponds to the first logic state during the power saving mode. ### Claim 7 A memory device operable at a first voltage domain and a second voltage domain, the memory device comprising: a memory array, configured to operate at the first voltage domain; a first logic circuit, configured to operate at the first voltage domain when the memory device is in a first power saving mode and to operate at the second voltage domain when the memory device is not in the first power saving mode; and a word line level shifter circuit, coupled to the memory array, configured to clamp a word line of the memory array to a predetermined voltage level that corresponds to a first logic state during the first power saving mode of the memory device. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the first logic circuit comprises: a first input terminal, receiving a first power saving mode enable signal; a second input terminal, receiving a second power saving mode enable signal; a third input terminal, receiving a third power saving mode enable signal; and an output terminal, configured to output a first control signal that is obtained by performing a first logic operation on the first power saving mode enable signal, the second power saving mode enable signal and the third power saving mode enable signal. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the memory device operates in the first power saving mode when the first power saving mode enable signal is in the second logic state, the memory device operates in a second power saving mode when the second power saving mode enable signal is in the second logic state, and the memory device operates in a third power saving mode when the third power saving mode enable signal is in the second logic state. ### Claim 10 (depends on 9) The memory device of claim 9, further comprising: a power switch, having a control terminal coupled to the first logic circuit and an output terminal coupled to a bus, configured to perform a switching operation according to the first control signal, wherein the power switch is configured to clamp the bus to the predetermined voltage level corresponding to the first logic state during the first power saving mode, the second power saving mode and the third power saving mode. ### Claim 11 (depends on 8) The memory device of claim 8, further comprising: a first level shifter, configured to convert the second power saving mode enable signal from the second voltage domain to the first voltage domain to generate a first shifted signal; a second level shifter, configured to convert the third power saving mode enable signal from the second voltage domain to the first voltage domain to generate a second shifted signal; and a second logic circuit, configured to receive the first shifted signal, the second shifted signal and the first power saving mode enable signal, and perform a second logic operation to the first shifted signal, the second shifted signal and the first power saving mode enable signal to generate a second control signal, wherein the second logic circuit operate in the first voltage domain and the first power saving mode enable signal is in the first voltage domain. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the word line level shifter circuit comprises: a first node; a first transistor, coupled to the first node, configured to clamp the first node to the first logic state during the first power saving mode, the second power saving mode and the third power saving mode of the memory device; a second node; and a second transistor, coupled to the first node and the second node, configured to clamp the second node to the second logic state during the first power saving mode, the second power saving mode and the third power saving mode of the memory device. ### Claim 13 (depends on 12) The memory device of claim 12, wherein the word line level shifter circuit further comprises: a third logic circuit, operated at the first voltage domain, having an input terminal coupled to the second node and an output terminal coupled to the word line, configured to clamp the word line to the predetermined voltage level that corresponds to the first logic state during the first power saving mode, the second power saving mode and the third power saving mode. ### Claim 14 (depends on 11) The memory device of claim 11, further comprising: a first power management circuit, coupled to the memory array, configured to supply a first voltage in the first voltage domain to the memory array during the first power saving mode and the third power saving mode and to stop supplying the first voltage to the memory array during the second power saving mode, wherein the power management circuit comprises: a first switch, coupled to the second logic circuit to receive the second control signal, configured to perform a switching operation based on the second control signal; and a second switch, coupled to the first level shifter to receive the first shifted signal, configured to perform a switching operation based on the first shifted signal. ### Claim 15 (depends on 7) The memory device of claim 7, further comprising: a second power supply circuit, coupled to the first logic circuit, configured to supply a first voltage in the first voltage domain to the first logic circuit when the first power saving mode is enabled and supply a second voltage in the second voltage domain to the first logic circuit when the power saving mode is disabled, wherein the power supply circuit comprises: an inverter, configured to receive the first power saving mode enable signal and generate an inverted signal of the first power saving mode enable signal; a third switch, having a control terminal configured to receive the first power saving mode enable signal, and configured to supply the second voltage in the second voltage domain to the first logic circuit when the power saving mode is disabled; and a fourth switch, having a control terminal configured to receive the inverted signal of the first power saving mode enable signal, and configured to supply the first voltage in the first voltage domain to the first logic circuit when the power saving mode is enabled. ### Claim 16 (depends on 7) The memory device of claim 7, wherein the first voltage domain is higher than the second voltage domain, and the predetermined voltage level corresponding to the first logic state is zero volt. ### Claim 17 A power management method, adapted to a memory device operable at a first voltage domain and a second voltage domain, the method comprising: determining whether the memory device operates in a power saving mode according to a power saving mode enable signal; and in response to determining that the memory device operates in the power saving mode, clamping a word line of a memory array to a predetermined voltage level that corresponds to a first logic state during the power saving mode. ### Claim 18 (depends on 17) The power management method of claim 17, further comprising: receiving the power saving mode enable signal from outside of the memory device through a power saving mode pin; determining that the memory device is not in the power saving mode when the power saving mode enable signal is in the first logic state; and determining that the memory device is not in the power saving mode when the power saving mode enable signal is in a second logic state. ### Claim 19 (depends on 17) The power management method of claim 17, wherein the word line is clamped to the predetermined voltage level that corresponds to the first logic state during the power saving mode by a word line level shifter circuit, and the word line level shifter circuit comprises: a first node; a first transistor, coupled to the first node, configured to clamp the first node to the first logic state during the power saving mode of the memory device; a second node; and a second transistor, coupled to the first node and the second node, configured to clamp the second node to the second logic state during the power saving mode of the memory device. ### Claim 20 (depends on 17) The power management method of claim 17, wherein clamping the word line of the memory array to the predetermined voltage level that corresponds to the first logic state during the power-saving mode comprises: turning on the first transistor during the power saving mode to clamp the first node to the first logic state during the power saving mode; turning on the second transistor during the power saving mode to clamp the first node to the second logic state during the power saving mode; and performing a logic operation on a signal in the second node to clamp the word line of the memory array to the first logic state during the power saving mode.