# US 2021/0241706 A1 · Shift register unit and driving method thereof, and gate driving circuit, display apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241706 A1 - Document ID: US20210241706A1 - Status: Published application - Kind: A1 - Application number: 16/650,593 - Filed: 2019-04-02 - Published: 2021-08-05 - Earliest claimed: 2019-04-02 - Assignees: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Chengdu Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Yao HUANG; Yang ZHOU; Gen LI - Web page: https://patentgrep.com/patent/US20210241706A1 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3614: {Control of polarity reversal in general} - G09G 3/3674: {Details of drivers for scan electrodes} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/061: for resetting or blanking - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Provided is shift register unit, a gate driving circuit, and a display apparatus. The shift register unit includes an input-sub-circuit, having a first terminal connected to an input signal terminal and a second terminal connected to a terminal of a first control signal; a first output sub-circuit, having a first terminal connected to a third terminal of the input sub-circuit, a second terminal connected to a terminal of a second control signal, and a third terminal connected to a first output terminal; a phase inversion control sub-circuit, having a first terminal connected to the first output terminal, a second terminal connected to a terminal of a third control signal; and a second output sub-circuit, having a first terminal connected to the first output terminal, a second terminal connected to a third terminal of the phase inversion control sub-circuit, and a third terminal connected to a second output terminal. ## Claims ### Claim 1 A shift register unit, comprising: an input-sub-circuit, having a first terminal connected to an input signal terminal and a second terminal connected to a terminal of a first control signal; a first output sub-circuit, having a first terminal connected to a third terminal of the input sub-circuit, a second terminal connected to a terminal of a second control signal, and a third terminal connected to a first output terminal; a phase inversion control sub-circuit, having a first terminal connected to the first output terminal, a second terminal connected to a terminal of a third control signal; and a second output sub-circuit, having a first terminal connected to the first output terminal, a second terminal connected to a third terminal of the phase inversion control sub-circuit, and a third terminal connected to a second output terminal; wherein the second output sub-circuit is configured that when a signal output by the first output sub-circuit changes from a valid level to an invalid level, a signal output by the second output sub-circuit changes from the invalid level to the valid level. ### Claim 2 (depends on 1) The shift register unit according to claim 1, further comprising: an output control sub-circuit, having a first terminal connected to the third terminal of the input sub-circuit, a second terminal connected to the terminal of the first control signal, and a third terminal connected to the first output terminal. ### Claim 3 (depends on 1) The shift register unit according to claim 1, further comprising: a reset sub-circuit, having a first terminal connected to the third terminal of the input sub-circuit, a second terminal connected to a fourth terminal of the output control sub-circuit. ### Claim 4 (depends on 1) The shift register unit according to claim 1, wherein the phase inversion control sub-circuit comprises: a first phase inversion control transistor, having a control electrode connected to the first output terminal, a first electrode connected to a terminal of an invalid level signal, and a second electrode connected to the second output sub-circuit; a second phase inversion control transistor, having a control electrode connected to the terminal of the third control signal, a first electrode connected to the second electrode of the first phase inversion control transistor, and a second electrode connected to a terminal of a valid level signal. ### Claim 5 (depends on 1) The shift register unit according to claim 1, wherein the input sub-circuit comprises: an input transistor, having a control terminal connected to the terminal of the first control signal, a first electrode connected to the input signal terminal, and a second electrode connected to the first terminal of the first output sub-circuit. ### Claim 6 (depends on 1) The shift register unit according to claim 1, wherein the first output sub-circuit comprises: a first output transistor, having a control terminal connected to the third terminal of the input sub-circuit, a first electrode connected to the first output terminal, and a second electrode connected to the terminal of the second control signal; a first output capacitor, having a first terminal connected to the first output terminal, a second terminal connected to the control terminal of the first output transistor. ### Claim 7 (depends on 1) The shift register unit according to claim 1, wherein the second output sub-circuit comprises: a second output transistor, having a control terminal connected to the first output terminal, a first electrode connected to a terminal of an invalid level signal, and a second electrode connected to the second output terminal; and a third output transistor, having a control terminal connected to the third terminal of the phase inversion control sub-circuit, a first electrode connected to the second output terminal, and a second electrode connected to a terminal of a valid level signal. ### Claim 8 (depends on 7) The shift register unit according to claim 7, wherein the second output sub-circuit further comprises: a second output capacitor, having a first terminal connected to the second output terminal, and a second terminal connected to the control terminal of the third output transistor. ### Claim 9 (depends on 2) The shift register unit according to claim 2, wherein the output control sub-circuit comprises: a first output control transistor, having a control terminal connected to the first control signal terminal, a first electrode connected to a terminal of a valid level signal, and a second electrode connected to a fourth terminal of the output control sub-circuit; a second output control transistor, having a control terminal connected to the second electrode of the first output control transistor, a first electrode connected to a terminal of an invalid level signal, and a second electrode connected to the first output terminal; an output control capacitor, having a first terminal connected to the terminal of the invalid level signal, a second terminal connected to the control terminal of the second output control transistor; and a third output control transistor, having a control terminal connected to the third terminal of the input sub-circuit, a first electrode connected to the second electrode of the first output control transistor, and a second electrode connected to the terminal of first control signal terminal. ### Claim 10 (depends on 3) The shift register unit according to claim 3, wherein the reset sub-circuit comprises: a first reset transistor, having a control terminal connected to the fourth terminal of the output control sub-circuit, a first electrode connected to a terminal of an invalid level signal; and a second reset transistor, having a control terminal connected to the terminal of the second control signal, a first electrode connected to a second electrode of the first reset transistor, and a second electrode connected to the third terminal of the input sub-circuit. ### Claim 11 (depends on 1) A gate driving circuit having N stages of shift register units cascaded connected, the shift register unit being the shift register unit according to claim 1, wherein, an input signal terminal of an i-th stage shift register unit is connected to a first output terminal of an i-1-th stage shift register unit, and N is an integer larger than 2, 1