# US 2021/0241663 A1 · Detection circuit of gate driver, array substrate, display device and detection method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241663 A1 - Document ID: US20210241663A1 - Status: Published application - Kind: A1 - Application number: 16/758,900 - Filed: 2019-09-27 - Published: 2021-08-05 - Earliest claimed: 2018-10-31 - Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Meng LI; Zhigang SONG - Web page: https://patentgrep.com/patent/US20210241663A1 ## CPC - G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3266: Details of drivers for scan electrodes - G11C 19/287: {Organisation of a multiplicity of shift registers} - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure discloses a detection circuit of a gate driver, an array substrate, a display device and a detection method thereof. Gate scanning signals of each of the signal output ends are derived to a detection signal line through signal deriving circuits, such that the gate scanning signals are transmitted to a discrimination circuit outside the array substrate. The discrimination circuit can acquire in real time and record the gate scanning signals, so as to detect the gate scanning signals in real time, and further rapidly diagnose whether the gate scanning signals are abnormal based on detection results, and rapidly locate the positions at which the gate scanning signals are abnormal, so as to timely troubleshoot the fault. ## Claims ### Claim 1 A detection circuit of a gate driver, comprising: a plurality of first signal deriving sub-circuits, wherein a control end of each first signal deriving sub-circuit is coupled with a control signal line, and an input end of the each first signal deriving sub-circuit is coupled with at least one signal output end of the gate driver; and a plurality of second signal deriving sub-circuits, wherein the plurality of second signal deriving sub-circuits are in one-to-one correspondence with the plurality of first signal deriving sub-circuits, a control end of each second signal deriving sub-circuit is coupled with an output end of a corresponding first signal deriving sub-circuit, the control end of the each second signal deriving sub-circuit is coupled with a signal output end which is coupled with the corresponding first signal deriving sub-circuit, and an output end of the each second signal deriving sub-circuit is coupled with a detection signal line. ### Claim 2 (depends on 1) The detection circuit of a gate driver of claim 1, wherein the plurality of second signal deriving sub-circuits are coupled with the same detection signal line; and timing sequences of gate scanning signals output by each of the at least one signal output end corresponding to the each second signal deriving sub-circuit which is coupled with the same detection signal line are not overlapped with each other. ### Claim 3 (depends on 1) The detection circuit of a gate driver of claim 1, wherein the gate driver comprises a plurality of cascaded shifting registers, each shifting register comprises at least two signal output ends, and respective signal output ends of the each shifting register are coupled with different detection signal lines. ### Claim 4 (depends on 1) The detection circuit of a gate driver of claim 1, wherein the each first signal deriving sub-circuit comprises a first switch transistor, a gate of the first switch transistor is coupled with the control signal line, a first electrode of the first switch transistor is coupled with a corresponding signal output end, and the second electrode of the first switch transistor is coupled with a corresponding second signal deriving sub-circuit. ### Claim 5 (depends on 1) The detection circuit of a gate driver of claim 1, wherein the each second signal deriving sub-circuit comprises a second switch transistor, a gate of the second switch transistor is coupled with a corresponding signal output end, a first electrode of the second switch transistor is coupled with the corresponding first signal deriving sub-circuit, and the second electrode of the second switch transistor is coupled with a corresponding detection signal line. ### Claim 6 (depends on 1) The detection circuit of a gate driver of claim 1, wherein respective first signal deriving sub-circuits are coupled with the same control signal line. ### Claim 7 (depends on 1) The detection circuit of a gate driver of claim 1, further comprising a discrimination circuit, and the discrimination circuit comprises: an analogue-to-digital conversion circuit configured to be coupled with the detection signal line; and a counting circuit configured to be coupled with the analogue-to-digital conversion circuit. ### Claim 8 (depends on 6) The detection circuit of a gate driver of claim 6, further comprising: a first control circuit, wherein a control end of the first control circuit is coupled with a first clock signal end, an input end of the first control circuit is coupled with a first reference signal end, and an output end of the first control circuit is coupled with one end of the control signal line; and a second control circuit, wherein a control end of the second control circuit is coupled with a second clock signal end, an input end of the second control circuit is coupled with a second reference signal end, and an output end of the second control circuit is coupled with the other end of the control signal line. ### Claim 9 (depends on 8) The detection circuit of a gate driver of claim 8, wherein the first control circuit comprises a third switch transistor, wherein a gate of the third switch transistor is coupled with the first clock signal end, a first electrode of the third switch transistor is coupled with the first reference signal end, and a second electrode of the third switch transistor is coupled with the control signal line. ### Claim 10 (depends on 8) The detection circuit of a gate driver of claim 8, wherein the second control circuit comprises a fourth switch transistor, wherein a gate of the fourth switch transistor is coupled with the second clock signal end, a first electrode of the fourth switch transistor is coupled with the second reference signal end, and a second electrode of the fourth switch transistor is coupled with the control signal line. ### Claim 11 (depends on 1) The detection circuit of a gate driver of claim 1, wherein the each first signal deriving sub-circuit comprises a first switch transistor, the each second signal deriving sub-circuit comprises a second switch transistor, wherein a gate of the first switch transistor is coupled with the control signal line, a first electrode of the first switch transistor and a gate of the second switch transistor are coupled with the same signal output end, a second electrode of the first switch transistor is coupled with a first electrode of the second switch transistor, and a second electrode of the second switch transistor is coupled with the corresponding detection signal line; the detection circuit further comprises a third switch transistor and a fourth switch transistor, wherein a gate of the third switch transistor is coupled with the first clock signal end, a first electrode of the third switch transistor is coupled with the first reference signal end, a second electrode of the third switch transistor is coupled with one end of the control signal line, a gate of the fourth switch transistor is coupled with the second clock signal end, a first electrode of the fourth switch transistor is coupled with a second reference signal end, and a second electrode of the fourth switch transistor is coupled with the other end of the control signal line. ### Claim 12 (depends on 1) An array substrate, comprising: a gate driver, comprising a plurality of signal output ends; a plurality of gate lines, wherein one of the plurality of gate lines is coupled with one of the plurality of signal output ends; a plurality of drive circuits arranged in an array, wherein one of the plurality of drive circuits is coupled with at least one gate line; and the detection circuit of claim 1. ### Claim 13 (depends on 12) The array substrate of claim 12, wherein the gate driver comprises a plurality of cascaded shifting registers, wherein each shifting register comprises two signal output ends which are respectively a first signal output end and a second signal output end; each drive circuit comprises: a fifth switch transistor, wherein a gate of the fifth switch transistor is coupled with the first signal output end through one gate line, and a source of the fifth switch transistor is coupled with a data line; a drive transistor, wherein a gate of the drive transistor is coupled with a drain of the fifth switch transistor, and a source of the drive transistor is coupled with a first supply voltage signal end; a sixth switch transistor, wherein a gate of the sixth switch transistor is coupled with the second signal output end through one gate line, a source of the sixth switch transistor is coupled with a drain of the drive transistor, and a drain of the sixth switch transistor is coupled with an induction signal line; a capacitor, coupled between the gate of the drive transistor and the drain of the drive transistor; and a to-be-driven element, coupled between the drain of the drive transistor and a second supply voltage signal end. ### Claim 14 (depends on 13) The array substrate of claim 13, wherein the first supply voltage signal end and the first reference signal end are the same signal end, and the second supply voltage signal end and the second reference signal end are the same signal end. ### Claim 15 (depends on 12) A display device, comprising the array substrate of claim 12. ### Claim 16 (depends on 15) A detection method of the display device of claim 15, comprising: controlling the plurality of signal output ends of the gate driver to output gate scanning signals in sequence; loading a first reference signal to the control signal line in a detection time period, wherein the first signal deriving sub-circuits transmit the gate scanning signals output by coupled signal output ends to the second signal deriving sub-circuits under the control of the first reference signal, and the second signal deriving sub-circuits transmit received gate scanning signals to a coupled detection signal line under the control of the gate scanning signals output by the coupled signal output ends; and performing, by the discrimination circuit, abnormality diagnosis on the gate scanning signals transmitted by the detection signal line. ### Claim 17 (depends on 16) The detection method of claim 16, wherein the performing by the discrimination circuit, abnormality diagnosis on the gate scanning signals transmitted by the detection signal line specifically comprises: converting, by an analogue-to-digital conversion circuit, the received gate scanning signals into digital signals; and accumulating, by a counting circuit, a quantity of pulses of received digital signals, to perform abnormality diagnosis on the gate scanning signals. ### Claim 18 (depends on 16) The detection method of claim 16, further comprising: in a non-detection stage, loading second reference signals to the control signal line; and disconnecting, by the first signal deriving sub-circuits, the signal output ends from the second signal deriving sub-circuits.