# US 2021/0241418 A1 · Workload scheduling and distribution on a distributed graphics device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241418 A1 - Document ID: US20210241418A1 - Status: Published application - Kind: A1 - Application number: 17/234,039 - Filed: 2021-04-19 - Published: 2021-08-05 - Earliest claimed: 2019-01-09 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Balaji Vembu; Brandon Fliflet; James Valerio; Michael Apodaca; Ben Ashbaugh; Hema Nalluri; Ankur Shah; Murali Ramadoss; David Puffer; Altug Koker; Aditya Navale; Abhishek R. Appu; Joydeep Ray; Travis Schluessler - Web page: https://patentgrep.com/patent/US20210241418A1 ## CPC - G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/5061: {Partitioning or combining of resources} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06T 1/60: Memory management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency. ## Claims ### Claim 1 A graphics processor comprising: a first tile of graphics processing resources; a second tile of graphics processing resources, the second tile of graphics processing resources including circuitry to accelerate a matrix operation; and an interface between a host system and the graphics processor, the interface to receive a set of commands for a workload having a first partition and a second partition, submit the set of commands to the first tile of graphics processing resources, and submit the set of commands to the second tile of graphics processing resources; wherein the first tile of graphics processing resources is to read a first partition identifier from a first hardware context, the first partition identifier associated with the first partition, and conditionally execute commands of the first partition while bypassing commands of the second partition; and wherein the second tile of graphics processing resources is to read a second partition identifier from a second hardware context, the second partition identifier associated with the second partition, and conditionally execute commands of the second partition while bypassing commands of the first partition, wherein to conditionally execute the commands of the second partition includes to execute a command associated with the matrix operation. ### Claim 2 (depends on 1) The graphics processor as in claim 1, the interface to the host system further to receive a command to associate the first hardware context with the first tile of graphics processing resources. ### Claim 3 (depends on 2) The graphics processor as in claim 2, the interface to the host system further to receive a command to configure the first hardware context based on a first logical render context. ### Claim 4 (depends on 3) The graphics processor as in claim 3, the interface to the host system further to receive a command to associate the second hardware context with the second tile of graphics processing resources. ### Claim 5 (depends on 4) The graphics processor as in claim 4, the interface to the host system further to receive a command to configure the second hardware context based on a second logical render context. ### Claim 6 (depends on 5) The graphics processor as in claim 5, wherein the interface is to receive the set of commands for the workload via a memory buffer including commands to be executed for the workload. ### Claim 7 (depends on 6) The graphics processor as in claim 6, wherein the first hardware context includes a first offset within the memory buffer associated with a start of the first partition, the second hardware context includes a second offset within the memory buffer associated with the start of the second partition, and the first hardware context and the second hardware context each include a step value associated with a number of partitions of the workload. ### Claim 8 (depends on 7) The graphics processor as in claim 7, wherein the first tile of graphics processing resources is to begin execution of commands for the first partition with a command stored at the first offset within the memory buffer. ### Claim 9 (depends on 7) The graphics processor as in claim 7, wherein the second tile of graphics processing resources is to begin execution of commands for the second partition with a command stored at the second offset within the memory buffer. ### Claim 10 (depends on 7) The graphics processor as in claim 7, wherein the first tile of graphics processing resources is to synchronize with the second tile of graphics processing resources when execution of the first partition and the second partition completes. ### Claim 11 A non-transitory machine-readable medium storing instructions which cause one or more processors to perform operations, wherein the one or more processors include a graphics processor and the operations comprise: receiving a set of commands for a workload having a first partition and a second partition; submitting the set of commands to a first tile of graphics processing resources of the graphics processor; submitting the set of commands to a second tile of graphics processing resources of the graphics processor, the second tile of graphics processing resources including circuitry to accelerate a matrix operation; at the first tile of graphics processing resources, reading a first partition identifier from a first hardware context, the first partition identifier associated with the first partition, and conditionally executing commands of the first partition while bypassing commands of the second partition; and at the second tile of graphics processing resources, reading a second partition identifier from a second hardware context, the second partition identifier associated with the second partition, and conditionally executing commands of the second partition while bypassing commands of the first partition, wherein conditionally executing the commands of the second partition includes executing a command associated with the matrix operation. ### Claim 12 (depends on 11) The non-transitory machine-readable medium as in claim 11, the operations further comprising: receiving a first command to associate the first hardware context with the first tile of graphics processing resources; and receiving a second command to associate the second hardware context with the second tile of graphics processing resources. ### Claim 13 (depends on 12) The non-transitory machine-readable medium as in claim 12, the operations further comprising: receiving a third command to configure the first hardware context based on a first logical render context; and receiving a fourth command to configure the second hardware context based on a second logical render context. ### Claim 14 (depends on 13) The non-transitory machine-readable medium as in claim 13, the operations further comprising receiving the set of commands for the workload via a memory buffer including commands to be executed for the workload. ### Claim 15 (depends on 14) The non-transitory machine-readable medium as in claim 14, wherein the first hardware context includes a first offset within the memory buffer associated with a start of the first partition, the second hardware context includes a second offset within the memory buffer associated with the start of the second partition, and the first hardware context and the second hardware context each include a step value associated with a number of partitions of the workload. ### Claim 16 A data processing system comprising: a host interconnect; and a graphics processor coupled with the host interconnect, the graphics processor including a first tile of graphics processing resources and a second tile of graphics processing resources, the second tile of graphics processing resources including circuitry to accelerate a matrix operation, wherein the graphics processor is configured to be presented to a host processor of the data processing system as a single device, and the graphics processor includes hardware circuitry to: receive, via the host interconnect, a set of commands for a workload having a first partition and a second partition; submit the set of commands to a first tile of graphics processing resources of the graphics processor; submit the set of commands to a second tile of graphics processing resources of the graphics processor; at the first tile of graphics processing resources, read a first partition identifier from a first hardware context, the first partition identifier associated with the first partition, and conditionally execute commands of the first partition while bypassing commands of the second partition; and at the second tile of graphics processing resources, read a second partition identifier from a second hardware context, the second partition identifier associated with the second partition, and conditionally execute commands of the second partition while bypassing commands of the first partition, wherein to conditionally execute the commands of the second partition includes to execute a command associated with the matrix operation. ### Claim 17 (depends on 16) The data processing system as in claim 16, the graphics processor further to: receive a first command to associate the first hardware context with the first tile of graphics processing resources; and receive a second command to associate the second hardware context with the second tile of graphics processing resources. ### Claim 18 (depends on 17) The data processing system as in claim 17, the graphics processor further to: receive a third command to configure the first hardware context based on a first logical render context; and receive a fourth command to configure the second hardware context based on a second logical render context. ### Claim 19 (depends on 18) The data processing system as in claim 18, the graphics processor further to: receive the set of commands for the workload via a memory buffer including commands to be executed for the workload; wherein the first hardware context includes a first offset within the memory buffer associated with a start of the first partition and the second hardware context includes a second offset within the memory buffer associated with the start of the second partition; wherein the first tile of graphics processing resources is to begin execution of commands for the first partition with a command stored at a first offset within the memory buffer; and wherein the second tile of graphics processing resources is to begin execution of commands for the second partition with a command stored at a second offset within the memory buffer. ### Claim 20 (depends on 19) The data processing system as in claim 19, wherein the first tile of graphics processing resources is to synchronize with the second tile of graphics processing resources when execution of the first partition and the second partition completes.