# US 2021/0241161 A1 · Frequency allocation in multi-qubit circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241161 A1 - Document ID: US20210241161A1 - Status: Published application - Kind: A1 - Application number: 17/240,095 - Filed: 2021-04-26 - Published: 2021-08-05 - Earliest claimed: 2018-06-07 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Jared Barney Hertzberg; Sami Rosenblatt; Easwar Magesan; John Aaron Smolin - Web page: https://patentgrep.com/patent/US20210241161A1 ## CPC - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 13/4068: {Electrical coupling} - G06N 10/00: Quantum computing, i.e. information processing based on quantum-mechanical phenomena - H10N 99/05: {Devices based on quantum mechanical effects, e.g. quantum interference devices or metal single-electron transistors} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations. ## Claims ### Claim 1 A system comprising: a memory that stores computer executable components; and a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise: a performance analysis component that analyzes simulated performance of respective qubit chip features and determines operation metrics for the respective qubit chip feature; and a design generation component that generates a superconducting qubit chip design using one or more of the respective qubit chip features based on respective operation metrics determined by the performance analysis component. ### Claim 2 (depends on 1) The system of claim 1, wherein the respective qubit chip features comprise at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus. ### Claim 3 (depends on 1) The system of claim 1, wherein the respective qubit chip features comprise at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits. ### Claim 4 (depends on 1) The system of claim 1, wherein the computer executable components further comprise: a collision monitoring component that defines frequency collision windows for respective qubits corresponding to the qubit chip features. ### Claim 5 (depends on 4) The system of claim 4, wherein the collision monitoring component identifies collisions between the respective qubits based on the frequency collision windows. ### Claim 6 (depends on 1) The system of claim 1, wherein the computer executable components further comprise: a fabrication component that fabricates a superconducting qubit chip according to the superconducting qubit chip design generated by the design generation component, wherein the superconducting qubit chip design generated by the design generation component results in improved resilience of the superconducting qubit chip to imperfections in fabrication by the fabrication component. ### Claim 7 A computer-implemented method comprising: determining, by a device operatively coupled to a processor, operation metrics for respective qubit chip features by analyzing simulated performance of the respective qubit chip features; and generating, by the device, a superconducting qubit chip design using one or more of the respective qubit chip features based on their respectively corresponding operation metrics. ### Claim 8 (depends on 7) The computer-implemented method of claim 7, wherein the determining comprises: defining, by the device, frequency collision windows for respective qubits corresponding to the qubit chip features. ### Claim 9 (depends on 7) The computer-implemented method of claim 7, wherein the determining comprises: identifying, by the device, collisions between the respective qubits based on the frequency collision windows. ### Claim 10 (depends on 7) The computer-implemented method of claim 7, wherein the generating results in a generated superconducting qubit chip design, further comprising: fabricating, by the device, a superconducting qubit chip according to the generated superconducting qubit chip design. ### Claim 11 (depends on 7) The computer-implemented method of claim 7, wherein the respective qubit chip features comprise at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus. ### Claim 12 (depends on 7) The computer-implemented method of claim 7, wherein the respective qubit chip features comprise at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits. ### Claim 13 (depends on 7) The computer-implemented method of claim 7, further comprising fabricating a superconducting qubit chip according to the superconducting qubit chip design generated by the design generation component, wherein the superconducting qubit chip design generated by the design generation component results in improved resilience of the superconducting qubit chip to imperfections in fabrication by the fabrication component. ### Claim 14 A computer program product for designing a superconducting qubit chip, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: determine, by a device operatively coupled to a processor, operation metrics for respective qubit chip features by analyzing simulated performance of the respective qubit chip features; and generate, by the device, a superconducting qubit chip design using one or more of the respective qubit chip features based on their respectively corresponding operation metrics. ### Claim 15 (depends on 14) The computer program product of claim 14, wherein the program instructions further cause the processor to: define, by the device, frequency collision windows for respective qubits corresponding to the qubit chip features. ### Claim 16 (depends on 14) The computer program product of claim 14, wherein the program instructions further cause the processor to: identify, by the device, collisions between the respective qubits based on the frequency collision windows. ### Claim 17 (depends on 14) The computer program product of claim 14, wherein the program instructions further cause the processor to: fabricate, by the device, a superconducting qubit chip according to the generated superconducting qubit chip design. ### Claim 18 (depends on 14) The computer program product of claim 14, wherein the respective qubit chip features comprise at least one of total number of qubits, functionality of respective qubits, or a number of qubits per bus. ### Claim 19 (depends on 14) The computer program product of claim 14, wherein the respective qubit chip features comprise at least one of operational frequency ranges for respective qubits or anharmonicity parameters associated with the respective qubits. ### Claim 20 (depends on 14) The computer program product of claim 14, wherein the program instructions further cause the processor to: fabricate a superconducting qubit chip according to the superconducting qubit chip design generated by the design generation component, wherein the superconducting qubit chip design generated by the design generation component results in improved resilience of the superconducting qubit chip to imperfections in fabrication by the fabrication component.