# US 2021/0241085 A1 · Method and architecture for accelerating deterministic stochastic computing using residue number system

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- Number: US 2021/0241085 A1
- Document ID: US20210241085A1
- Status: Published application
- Kind: A1
- Application number: 17/166,378
- Filed: 2021-02-03
- Published: 2021-08-05
- Earliest claimed: 2020-02-04
- Assignees: University of Louisiana at Lafayette
- Applicants: University of Louisiana at Lafayette
- Inventors: Mohammadhassan Najafi; Kamyar Givaki; Seyed Reza Hojabrossadati; M.H. Gholamrezayi; Ahmad Khonsari; Saeid Gorgin; Dara Rahmati
- Web page: https://patentgrep.com/patent/US20210241085A1

## CPC

- G06N 3/063: using electronic means
- G06F 1/3234: Power saving characterised by the action undertaken
- G06F 7/729: {using representation by a residue number system}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/08: Learning methods
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- G06N 3/045: Combinations of networks
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Inaccuracy of computations is an important challenge with the Stochastic Computing (SC) paradigm. Recently, deterministic approaches to SC are proposed to produce completely accurate results with SC circuits. Instead of random bit-streams, the computations are performed on structured deterministic bit-streams. However, current deterministic methods take a large number of clock cycles to produce correct result. This long processing time directly translates to very high energy consumption. This invention proposes a design methodology based on the Residue Number Systems (RNS) to mitigate the long processing time of the deterministic methods. Compared to the state-of-the-art deterministic methods of SC, the proposed approach delivers improvements in terms of processing time and energy consumption.

## Claims

### Claim 1

An architecture for performing bit-stream processing, comprising:
(a) at least one finite state machine;
(b) at least one bit-stream generator;
(c) a moduli set;
(d) at least one input buffer, which stores at least two numbers;
(e) at least one counter;
(f) at least one AND gate; and
(g) a controller;
wherein the stored at least two numbers function as inputs for the architecture;
wherein the stored at least two numbers are stored in Residue Number System format; and
wherein the at least one bit-stream generator comprises coding capable of converting one or more residues of the at least two numbers to bit-stream representation.

### Claim 2 (depends on 1)

The architecture of claim 1, wherein the stored at least two numbers comprise three residues.

### Claim 3 (depends on 1)

The architecture of claim 1, further comprising one or more multiplexer units.

### Claim 4 (depends on 1)

The architecture of claim 1, further comprising at least one multiplexer for each residue to be converted.

### Claim 5 (depends on 1)

The architecture of claim 1, wherein the finite state machines are connected an input of at least one or more multiplexer units.

### Claim 6 (depends on 1)

The architecture of claim 1, further comprising at least one additional finite state machine, and wherein the finite state machines are configured to generate different low-discrepancy patterns.

### Claim 7 (depends on 1)

The architecture of claim 1, wherein the stored at least two numbers comprise three residues, and further comprising three parallel AND gates where each AND gate is connected to at least one bit-stream generator.

### Claim 8 (depends on 1)

The architecture of claim 1, wherein each of the at least one AND gate is connected to one of the at least one counter.

### Claim 9 (depends on 1)

The architecture of claim 1, wherein the at least one counters store one or more results of the bit-stream processing.

### Claim 10 (depends on 1)

The architecture of claim 1, further comprising a Reverse Converter.

### Claim 11 (depends on 1)

The architecture of claim 1, further comprising a Reverse Converter comprising a Look-Up Table.

### Claim 12

A method for performing bit-stream processing, comprising:
storing at least two distinct numbers in an input buffer;
inputting the at least two distinct numbers into an at least one bit-stream generator;
generating one or more deterministic bit-streams by the at least one bit-stream generator;
performing multiplication of one or more outputs of the at least one bit-stream generator using an AND gate to produce a bit-stream;
converting the produced bit-stream to binary representation using a counter; and
calculating any residues.

### Claim 13 (depends on 12)

The method of claim 12, wherein the at least two distinct numbers are stored in Residue Number System format.

### Claim 14 (depends on 12)

The method of claim 12, wherein the converting the produced bit-stream to weighted binary format occurs last.

### Claim 15 (depends on 12)

The method of claim 12, wherein the produced bit-stream is converted to binary representation through the counter counting how many 1s are found in the produced bit-stream.

### Claim 16 (depends on 12)

The method of claim 12, further comprising converting the produced bit-stream to weighted binary format.