# US 2021/0241084 A1 · Neural network unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241084 A1 - Document ID: US20210241084A1 - Status: Published application - Kind: A1 - Application number: 17/163,513 - Filed: 2021-01-31 - Published: 2021-08-05 - Earliest claimed: 2020-02-03 - Assignees: Anaflash Inc. - Applicants: Anaflash Inc. - Inventors: Seung-Hwan Song - Web page: https://patentgrep.com/patent/US20210241084A1 ## CPC - G06N 3/063: using electronic means - G06N 3/065: Analogue means - G06N 3/04: Architecture, e.g. interconnection topology - G06N 3/0499: Feedforward networks - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A neural network unit is disclosed. This neural network unit includes: a main synapse array having a plurality of main synapses in rows and columns of the array, each connected to one or more bit lines associated with the network unit; a main synapse driver for applying an input to one or more of the main synapses in a row; a reference synapse for generating a particular output to a selected one or more associated bit lines; and, a sensing circuit for controlling the reference synapse in generating the output in a selected column of the array, wherein the sensing circuit is adapted to infer an output from one or more main synapses in a selected column by: defining a reference range of the output to be generated by reference synapse; setting a reference level from the reference range; activating a selected reference synapse to implement the reference level that is set or adjusted; and comparing an output from the main synapse summed with the output from the activated reference synapse in the selected column with a threshold value predetermined. ## Claims ### Claim 1 A neural network unit, comprising: a main synapse array having a plurality of main synapses in rows and columns of the array, each connected to one or more bit lines associated with the network unit; a main synapse driver for applying an input to one or more of the main synapses in a row; a reference synapse for generating a particular output to a selected one or more associated bit lines; and, a sensing circuit for controlling the reference synapse in generating the output in a selected column of the array, wherein the sensing circuit is adapted to infer an output from one or more main synapses in a selected column by: defining a reference range of the output to be generated by reference synapse; setting a reference level from the reference range; activating a selected reference synapse to implement the reference level that is set or adjusted; and comparing an output from the main synapse summed with the output from the activated reference synapse in the selected column with a threshold value predetermined. ### Claim 2 (depends on 1) The neural network of claim 1, wherein the sensing circuit is further configured to perform the steps of: (a) adjusting the reference range to a sub-range depending on the comparison result; (b) adjusting the reference level to an approximated middle of the adjusted reference range; (c) comparing a summed output including an output corresponding to the adjusted reference level from the selected reference synapse with the threshold value; and (d) repeating steps (a) to (c) according to a specified number of times or until the inferred output refined through the repeating steps reaches a target resolution specified. ### Claim 3 (depends on 2) The neural network of claim 2, wherein the sensing circuit is further configured to adjust the reference range to a lower sub-range if the summed output is equal to or greater than the threshold value, or otherwise adjust the reference range to a higher sub-range. ### Claim 4 (depends on 1) The neural network of claim 1, wherein the main synapse driver is further configured to serially apply a plurality of voltage input sequences corresponding to an input data to one or more of the main synapses in the row. ### Claim 5 (depends on 4) The neural network of claim 4, wherein the sensing circuit is further configured to: receive an output current from one or more of the main synapses via a connected bit line in the selected column; set a reference range of the output current generated by the reference synapse that a binary search scheme to apply; define a reference level from the reference range; set none, one or more current sources in the selected reference synapse to generate an output corresponding to the reference level; compare an output current from the main synapse summed with the output current from the selected reference synapse in the column with a threshold value specified; and convert the comparison result into a corresponding binary signal. ### Claim 6 (depends on 5) The neural network of claim 5, wherein the sensing circuit is further configured to perform the steps of: (a) adjusting the reference range to a sub-range depending on the comparison result; (b) adjusting the reference level to an approximate middle of the adjusted reference range; (c) comparing a summed output current including an output current corresponding to the adjusted reference level from the selected reference synapse with the threshold value; and (d) repeating steps (a) to (c) according to the specified number of times or until the inferred output refined through the repeating steps reaches a target resolution specified. ### Claim 7 A neural network unit, comprising: a main synapse array having a plurality of main synapses in rows and columns of the array, each main synapse for producing a differential output pair connected to one or more pairs of bit lines associated with the network unit; a main synapse driver for applying a pair of input to the one or more main synapses in a row, a reference synapse for generating a particular pair of outputs to a selected one or more associated pairs of bit lines; and a sensing circuit for controlling the reference synapse in generating the pair of outputs: defining a reference range of the output to be generated by reference synapse; setting a pair of reference levels from the reference range; activating the selected reference synapse to implement the reference level that is set or adjusted; and comparing a first and a second output of the differential output pair, wherein each accumulated output includes the corresponding output from the main synapse and the output from a reference synapse selected. ### Claim 8 (depends on 7) A neural network of claim 7, wherein the sensing circuit adapted to infer the difference of a pair of the outputs by further implementing steps of: (a) adjusting the reference range to a sub-range depending on the comparison result, (b) adjusting the reference level to an approximated middle of the adjusted range, (c) comparing a first and second output of the differential output pair, each output generated by the main synapse summed with an output corresponding to the adjusted reference level, and (d) repeating steps (a) to (c) according to a specified number of times or until the inferred output refined through the repeating steps reaches a target resolution specified. ### Claim 9 (depends on 8) The neural network of claim 8, wherein the sensing circuit is adapted to infer the difference of a pair of the outputs by further implementing a step of adjusting the reference range to a lower sub-range if the first output is equal to or greater than the second output, or otherwise adjust the reference range to a higher sub-range. ### Claim 10 (depends on 9) The neural network of claim 9, wherein the main synapse driver is further configured to serially apply a plurality of voltage input sequences corresponding to a plurality of input data to the one or more synapses in the row. ### Claim 11 (depends on 10) The neural network of claim 10, wherein the sensing circuit is further configured to: receive an output current from one or more of the main synapses via the associated bit line in the selected column; set a reference range of the output current generated by the reference synapse that a binary search scheme to apply; define a reference level from the reference range; set none, one or more current sources in the selected reference synapse to generate an output corresponding to the reference level; compare an output current from the main synapse summed with the output current from the selected reference synapse with a threshold current value specified; and convert the comparison result into a corresponding binary signal. ### Claim 12 A method for inferring an output from a synapse array, comprising: receiving an output of one or more main synapses in each selected column of the synapse array; defining a reference range of an output to be generated by a reference synapse in the selected column; setting a reference level from the defined reference range; activating the selected reference synapse to implement the reference level that is set or adjusted; and comparing a sum of an output from the main synapse and an output from the activated reference synapse with a threshold value predefined. ### Claim 13 (depends on 12) A method of claim 12, further comprising: (a) adjusting the reference range to a sub-range depending on the comparison result; (b) adjusting the reference level to an approximated middle of the adjusted range; (c) comparing a summed output including an output corresponding to the adjusted reference level from the selected column synapses with the threshold value; and (d) repeating steps (a) to (c) according to a specified number of times or until an inferred output refined through the repeating steps reaches a target resolution specified. ### Claim 14 (depends on 13) The method of claim 13, further comprising adjusting the reference range to a lower sub-range if the summed output is equal to or greater than the threshold value, or otherwise adjusting the reference range to a higher sub-range. ### Claim 15 (depends on 12) The method of claim 12, the one or more of the main synapses is configured to receive a plurality of voltage input sequence from a main synapse driver connected to the synapse array, wherein the main synapse driver is configured to serially apply the plurality of voltage input sequences corresponding to an input data to one or more of the main synapses in the row. ### Claim 16 (depends on 12) The method of claim 12, further comprising generating an output sequence depending on the comparison result of the summed output to the threshold value. ### Claim 17 A method for inferring a differential output from a synapse array, comprising: receiving first and second outputs from one or more main synapses in a synapse array via one or more associated bit lines; defining a reference range of an output to be generated by a reference synapse connected to the one or more synapses; setting a reference level from the reference range; activating the selected reference synapse to produce an output corresponding to the reference level that is set or adjusted; and comparing first and second accumulated outputs, wherein each accumulated output includes the corresponding output from the main synapse and the output from a reference synapse selected. ### Claim 18 (depends on 17) The method of claim 17, further comprising: (a) adjusting the reference range to a sub-range depending on the comparison result, (b) adjusting the reference level to an approximated middle of the adjusted range, (c) comparing a first and second accumulated output of the differential output pair, one of the accumulated outputs generated by the main synapse summed with an output corresponding to the adjusted reference level, and, (d) repeating steps (a) to (c) according to a specified number of times or until the inferred difference refined through the repeating steps reaches a target resolution specified. ### Claim 19 (depends on 18) The neural network of claim 18, further comprising adjusting the reference range to a lower sub-range if the first accumulated output is equal to or greater than the second accumulated output, or otherwise adjusting the reference range to a higher sub-range. ### Claim 20 (depends on 17) The method of claim 17, wherein a main synapse driver associated with the synapse array is configured to serially apply a plurality of voltage input sequences corresponding to a plurality of input data to one or more of the main synapses in the row.