# US 2021/0241079 A1 · Broadcasting mode of planar engine for neural processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0241079 A1 - Document ID: US20210241079A1 - Status: Published application - Kind: A1 - Application number: 16/781,824 - Filed: 2020-02-04 - Published: 2021-08-05 - Earliest claimed: 2020-02-04 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: CHRISTOPHER L. MILLS; KENNETH W. WATERS; YOUCHANG KIM - Web page: https://patentgrep.com/patent/US20210241079A1 ## CPC - G06F 7/544: for evaluating functions by calculation {(G06F7/4824 takes precedence)} - G06N 3/063: using electronic means - G06F 7/78: for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor - G06F 9/542: {Event management; Broadcasting; Multicasting; Notifications} - G06N 3/045: Combinations of networks - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/084: Backpropagation, e.g. using gradient descent - G06N 20/10: using kernel methods, e.g. support vector machines [SVM] - G06F 2207/4824: Neural networks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract Embodiments relate to a neural processor that includes one or more neural engine circuits and planar engine circuits. The neural engine circuits can perform convolution operations of input data with one or more kernels to generate outputs. The planar engine circuit is coupled to the plurality of neural engine circuits. A planar engine circuit can be configured to multiple modes. In an elementwise mode, the planar engine circuit may combine two tensors by performing operations element by element. The planar engine circuit may support elementwise operation for two tensors that are in different sizes and ranks. The planar engine circuit may perform a broadcasting operation to duplicate one or more values across one or more channels to make a smaller tensor matching the size of the larger tensor. ## Claims ### Claim 1 A neural processor, comprising: a plurality of neural engine circuits, at least one of the neural engine circuits configured to perform a convolution operation of first input data with one or more kernels to generate a first output; and a planar engine circuit coupled to the plurality of neural engine circuits, the planar engine circuit configured to: receive second input data corresponding to the first output or a version of the first input data of the neural processor, perform a broadcasting operation on a version of the second input data to generate a processed second input data by at least duplicating a first value of the second input data across a first dimension, and perform an elementwise operation on the processed second input data to generate a second output. ### Claim 2 (depends on 1) The neural processor of claim 1, wherein the broadcasting operation is further performed by duplicating the value of the second input data across a second dimension. ### Claim 3 (depends on 1) The neural processor of claim 1, wherein the version of the second input data is a transposed version of the second input data. ### Claim 4 (depends on 3) The neural processor of claim 3, wherein the planar engine circuit is further configured to: perform a reversed transpose to the second output. ### Claim 5 (depends on 1) The neural processor of claim 1, wherein the second input data is a vector and the processed second input data has a higher rank than the vector. ### Claim 6 (depends on 1) The neural processor of claim 1, wherein the planar engine circuit is further configured to: receive a third input data, and the processed second input data having a ranking that is the same as the third input data, wherein the elementwise operation is performed to combine the third input data and the processed second input data to generate the second output. ### Claim 7 (depends on 1) The neural processor of claim 1, wherein the elementwise operation includes one or more tensor addition, elementwise maximum, elementwise minimum, or elementwise multiplication. ### Claim 8 (depends on 1) The neural processor of claim 1, wherein the planar engine circuit comprises one or more demultiplexer circuits, wherein the planar engine circuit is configured to perform the broadcasting operation by using the one or more demultiplexer circuits to duplicate the first value across the first dimension. ### Claim 9 (depends on 1) The neural processor of claim 1, further comprising a buffer coupled to the plurality of neural engine circuits and the planar engine circuit, the buffer configured to store the second input data, wherein the planar engine circuit is configured to perform the broadcasting operation by repeatedly fetching the first value from the buffer. ### Claim 10 (depends on 9) The neural processor of claim 9, wherein the planar engine circuit comprises one or more demultiplexer circuits, wherein the planar engine circuit is configured to perform the broadcasting operation further by using the one or more demultiplexer circuits to duplicate a second value across a second dimension different form the first dimension. ### Claim 11 (depends on 1) The neural processor of claim 1, wherein the planar engine circuit comprises a format converter configured to perform one or more format conversions on the second input data to generate the version of the second input data. ### Claim 12 A method for operating a neural processor, the method comprising: transmitting first input data to at least one of a plurality of neural engine circuits of the neural processor; performing, using the at least one of the plurality of neural engine circuits, a convolution operation of the first input data with one or more kernels to generate a first output; transmitting second input data to a planar engine circuit of the neural processor, the planar engine circuit coupled to the plurality of neural engine circuits, the second input data corresponding to the first output or a version of the first input data of the neural processor; performing a broadcasting operation on a version of the second input data to generate a processed second input data by at least duplicating a first value of the second input data across a first dimension; and performing an elementwise operation on the processed second input data to generate a second output. ### Claim 13 (depends on 12) The method of claim 12, further comprising: duplicating, in the broadcasting operation, the value of the second input data across a second dimension. ### Claim 14 (depends on 12) The method of claim 12, wherein the version of the second input data is a transposed version of the second input data. ### Claim 15 (depends on 12) The method of claim 12, wherein the second input data is a vector and the processed second input data has a higher rank than the vector. ### Claim 16 (depends on 12) The method of claim 12, further comprising: transmitting third input data to the planar engine circuit, and the processed second input data having a ranking that is the same as the third input data, wherein the elementwise operation is performed to combine the third input data and the processed second input data to generate the second output. ### Claim 17 (depends on 12) The method of claim 12, wherein the neural processor further comprises a buffer coupled to the plurality of neural engine circuits and the planar engine circuit, the buffer storing the second input data, wherein performing the broadcasting operation comprises repeatedly fetching the first value from the buffer. ### Claim 18 (depends on 12) The method of claim 12, wherein the planar engine circuit comprises one or more demultiplexer circuits, wherein performing the broadcasting operation comprises using the one or more demultiplexer circuits to duplicate the first value across the first dimension. ### Claim 19 An electronic device, comprising: a memory storing a machine learning model; and a neural processor, comprising: a plurality of neural engine circuits, at least one of the neural engine circuits configured to perform a convolution operation of first input data with one or more kernels to generate a first output; and a planar engine circuit coupled to the plurality of neural engine circuits, the planar engine circuit configured to: receive second input data corresponding to the first output or a version of the first input data of the neural processor, perform a broadcasting operation on a version of the second input data to generate a processed second input data by at least duplicating a first value of the second input data across a first dimension, and perform an elementwise operation on the processed second input data to generate a second output. ### Claim 20 (depends on 19) The electronic device of claim 19, wherein the convolution operation is one of a plurality of operations for implementing a machine learning model.