# US 2021/0240945 A1 · Resistive and digital processing cores

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- Number: US 2021/0240945 A1
- Document ID: US20210240945A1
- Status: Published application
- Kind: A1
- Application number: 17/049,031
- Filed: 2018-04-30
- Published: 2021-08-05
- Earliest claimed: 2018-04-30
- Assignees: Hewlett Packard Enterprise Development LP
- Applicants: Hewlett Packard Enterprise Development LP
- Inventors: John Paul STRACHAN; Dejan S. MILOJICIC; Martin FOLTIN; Sai Rahul CHALAMALASETTI; Amit S. SHARMA
- Web page: https://patentgrep.com/patent/US20210240945A1

## CPC

- G06J 1/00: Hybrid computing arrangements
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G06J: HYBRID COMPUTING ARRANGEMENTS (optical hybrid computing devices G06E3/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

## Claims

### Claim 1

A device comprising:
a first processing core comprising a resistive memory array to perform an analog computation;
a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions; and
a controller to selectively apply input data to the first processing core and the digital processing core.

### Claim 2 (depends on 1)

The device of claim 1, wherein the digital memory of the digital processing core comprises a random access memory.

### Claim 3 (depends on 2)

The device of claim 2, wherein the controller is to:
program the digital memory with first values to perform a first computation; and
program the digital memory with second values different from the first values to perform a second computation.

### Claim 4 (depends on 3)

The device of claim 3, wherein the first and second computations are different matrix operations.

### Claim 5 (depends on 4)

The device of claim 4, wherein the analog computation is a matrix operation involving a matrix programmed as values in resistive memory cells of the resistive memory array.

### Claim 6 (depends on 2)

The device of claim 2, wherein the random access memory comprises a static random access memory or a dynamic random access memory.

### Claim 7 (depends on 1)

The device of claim 1, wherein the digital processing core further comprises digital mathematical logic to perform a mathematical operation in a digital domain.

### Claim 8 (depends on 1)

The device of claim 1, further comprising:
a second processing core comprising a resistive memory array to perform an analog computation; and
a storage medium to store machine-readable instructions that upon execution performs a dynamic data process that causes the controller to selectively apply respective input data to the first processing core, the second processing core, and the digital processing core during the dynamic data process.

### Claim 9

A method comprising:
during performance of a dynamic data process:
selecting, by a controller, a first processing core comprising a resistive memory array to perform an analog computation;
in response to a first condition, programming, by the controller, first values into a digital memory of a digital processing core to perform a first computation; and
in response to a second condition, programming, by the controller, second values different from the first values into the digital memory of the digital processing core to perform a second computation different from the first computation.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first values and the second values correspond to different matrices, and the first and second computations comprise different matrix operations using respective matrices of the different matrices.

### Claim 11 (depends on 9)

The method of claim 9, wherein the analog computation uses values programmed in resistive memory cells of the resistive memory array.

### Claim 12 (depends on 11)

The method of claim 11, wherein the values programmed in the resistive memory cells of the resistive memory array remain static during the dynamic data process.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
pre-programming the values in the resistive memory cells of the resistive memory array prior to performing the dynamic data process.

### Claim 14 (depends on 9)

The method of claim 9, further comprising:
during the performance of the dynamic data process that includes a set of operations:
identifying, by the controller, operations of the set of operations to be performed by processing cores comprising respective resistive memory arrays; and
identifying, by the controller, a conditional operation of the set of operations to be performed by the digital processing core.

### Claim 15 (depends on 9)

The method of claim 9, wherein programming the digital memory of the digital processing core comprises writing values used in the first computation or the second computation.

### Claim 16 (depends on 9)

The method of claim 9, wherein the digital memory comprises a random access memory having a write access speed greater than a write access speed of the resistive memory array.

### Claim 17

A system comprising:
a plurality of integrated circuit devices;
a communication interconnect that interconnects the plurality of integrated circuit devices,
wherein a first integrated circuit device of the plurality of integrated circuit devices comprises:
a first processing core comprising a resistive memory array to perform an analog computation;
a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions; and
a controller to selectively apply input data to the first processing core and the digital processing core.

### Claim 18 (depends on 17)

The system of claim 17, wherein the first integrated circuit device comprises a plurality of tiles, wherein a first tile of the plurality of tiles comprises the first processing core, the digital processing core, and the controller.

### Claim 19 (depends on 18)

The system of claim 18, wherein a second tile of the plurality of tiles comprises:
a second processing core comprising a resistive memory array to perform an analog computation;
a second digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions; and
a controller to selectively apply input data to the second processing core and the second digital processing core.

### Claim 20 (depends on 17)

The system of claim 17, wherein the digital processing core further comprises a digital mathematical logic to perform a mathematical operation using values programmed in the digital memory.