# US 2021/0240907 A1 · Method and Apparatus for Integrated Circuit Mask Patterning

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- Number: US 2021/0240907 A1
- Document ID: US20210240907A1
- Status: Published application
- Kind: A1
- Application number: 17/236,832
- Filed: 2021-04-21
- Published: 2021-08-05
- Earliest claimed: 2013-08-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chin-Min Huang; Bo-Han Chen; Cherng-Shyan Tsay; Chien-Wen Lai; Hua-Tai Lin; Chia-Cheng Chang; Lun-Wen Yeh; Shun-Shing Yang
- Web page: https://patentgrep.com/patent/US20210240907A1

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G03F 1/70: Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)

## Abstract

Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

## Claims

### Claim 1

An integrated circuit (IC) mask comprising:
two disconnected IC sub-features that correspond with an IC feature to be formed on a wafer by a lithography process using the IC mask, wherein a first one of the two disconnected IC sub-features is spaced from a second one of the two disconnected IC sub-features by a width; and
the width is sub-resolution for the lithography process, such that the IC feature does not include the width when formed on the wafer by the lithography process using the IC mask.

### Claim 2 (depends on 1)

The IC mask of claim 1, wherein the two disconnected IC sub-features and the width have a combined contour that is different than a contour of the IC feature.

### Claim 3 (depends on 1)

The IC mask of claim 1, wherein:
the IC feature has a first segment, a second segment, and a third segment that connects the first segment to the second segment;
the first one of the two disconnected IC sub-features has a fourth segment that corresponds with the first segment and a first sub-segment connected to the fourth segment that corresponds with the third segment; and
the second one of the two disconnected IC sub-features has a fifth segment that corresponds with the second segment and a second sub-segment connected to the fifth segment that corresponds with the third segment, wherein the second sub-segment is spaced from the first sub-segment by the width.

### Claim 4 (depends on 3)

The IC mask of claim 3, wherein:
the first segment has a first contour;
the second segment has a second contour; and
the fourth segment has a third contour different than the first contour and the fifth segment has a fourth contour different than the second contour.

### Claim 5 (depends on 3)

The IC mask of claim 3, wherein:
the fourth segment and the fifth segment each have a center portion disposed between a first end portion and a second end portion; and
the center portion has a first width, the first end portion and the second end portion have a second width, and the first width is different than the second width.

### Claim 6 (depends on 5)

The IC mask of claim 5, wherein the first width is less than the second width.

### Claim 7 (depends on 5)

The IC mask of claim 5, wherein the first segment and the second segment each have a third width, the first width is less than the third width, and the second width is about the same as the third width.

### Claim 8 (depends on 3)

The IC mask of claim 3, wherein:
the width is a first width;
the fourth segment has a second width;
the first sub-segment has a third width that is less than the second width; and
the second sub-segment has a fourth width that is less than the second width.

### Claim 9 (depends on 8)

The IC mask of claim 8, wherein the third width is the same as the fourth width.

### Claim 10 (depends on 1)

The IC mask of claim 1, wherein the lithography process is an extreme ultraviolet (EUV) lithography process and the IC mask is an EUV mask.

### Claim 11

An integrated circuit (IC) mask comprising:
a first sub-feature separated from a second sub-feature by a spacing, wherein the first sub-feature, the spacing, and the second sub-feature correspond with an IC feature of a plurality of IC features to be formed on a wafer by a lithography process using the IC mask; and
wherein the spacing has a sub-resolution dimension, such that a printed IC feature that corresponds with the IC feature does not include the spacing when formed on the wafer by the lithography process using the IC mask.

### Claim 12 (depends on 11)

The IC mask of claim 11, wherein a combined contour of the first sub-feature, the second sub-feature, and the spacing is different than a contour of the IC feature.

### Claim 13 (depends on 11)

The IC mask of claim 11, wherein the IC feature is an H-shaped feature, the spacing corresponds with a removed portion of a horizontal line of the H-shaped feature, the first sub-feature corresponds with a left vertical line and a remaining left horizontal portion of the H-shaped feature, and the second sub-feature corresponds with a right vertical line and a remaining right horizontal portion of the H-shaped feature.

### Claim 14 (depends on 13)

The IC mask of claim 13, wherein:
the first sub-feature has a first portion that corresponds with the left vertical line and a second portion that extends from the first portion and corresponds with the remaining left horizontal portion; and
the second sub-feature has a third portion that corresponds with the right vertical line and a fourth portion that extends from the third portion and corresponds with the remaining right horizontal portion, wherein the spacing is between the second portion of the first sub-feature and the fourth portion of the second sub-feature.

### Claim 15 (depends on 14)

The IC mask of claim 14, wherein the second portion of the first sub-feature and the fourth portion of the second sub-feature each have a first width that is less than a second width of the horizontal line of the H-shaped feature.

### Claim 16 (depends on 14)

The IC mask of claim 14, wherein:
the first portion of the first sub-feature has a first width that varies along a first length of the first portion of the first sub-feature; and
the third portion of the second sub-feature has a second width that varies along a second length of the third portion of the second sub-feature.

### Claim 17 (depends on 16)

The IC mask of claim 16, wherein a first variation of the first width is the same as a second variation of the second width.

### Claim 18 (depends on 11)

The IC mask of claim 11, wherein the first sub-feature and the second sub-feature are a portion of a patterned layer of the IC mask, wherein the patterned layer includes opaque regions and transparent regions.

### Claim 19

An integrated circuit (IC) mask comprising:
a first polygon sub-feature separated from a second polygon sub-feature by a sub-resolution distance, wherein:
the first polygon sub-feature, the second polygon sub-feature, and the sub-resolution distance correspond with a polygon of an IC design layout, wherein the sub-resolution distance corresponds with a removed portion of the polygon; and
a shape of an IC feature formed on a wafer using the IC mask having the first polygon sub-feature separated from the second polygon sub-feature by the sub-resolution distances is substantially the same as a shape of the polygon of the IC design layout.

### Claim 20 (depends on 19)

The IC mask of claim 19, wherein the polygon has an H-shaped profile.