# US 2021/0240906 A1 · Integrated Circuit Layout Validation Using Machine Learning

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- Number: US 2021/0240906 A1
- Document ID: US20210240906A1
- Status: Published application
- Kind: A1
- Application number: 17/233,699
- Filed: 2021-04-19
- Published: 2021-08-05
- Earliest claimed: 2019-09-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Rachid Salik; Chin-Chang Hsu; Cheng-Chi Wu; Chien-Wen Chen; Wen-Ju Yang
- Web page: https://patentgrep.com/patent/US20210240906A1

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06T 7/001: {using an image reference approach}
- G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/08: Learning methods
- G06N 3/09: Supervised learning
- G06N 20/00: Machine learning
- G06T 7/0004: {Industrial image inspection}
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- G06T 2207/10061: from scanning electron microscope
- G06T 2207/20084: Artificial neural networks [ANN]
- G06T 2207/30148: Semiconductor; IC; Wafer
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

## Claims

### Claim 1

A computer-implemented method comprising:
generating, by a machine learning model, a prediction model for validating IC layouts;
receiving, by the prediction model, data comprising a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns;
determining, by the prediction model, design violations associated with an IC layout based on the SEM images and the plurality of IC patterns by:
generating a compilation of pixel patterns including a first set of pixel patterns capable of being manufactured and a second set of pixel patterns incapable of being manufactured; and
identifying differences between the IC layout with the first set of pixel patterns and the second set of pixel patterns, wherein the design violations comprise the differences; and
providing a summary of the design violations for further characterization of the IC layout.

### Claim 2 (depends on 1)

The computer-implemented method of claim 1, wherein the design violations are further determined by:
receiving the IC layout for validation.

### Claim 3 (depends on 1)

The computer-implemented method of claim 1, further comprising:
determining, by the machine learning model, a confidence score associated with the determination of design violations;
identifying, based on the confidence score being below a threshold, a new pattern not belonging to the first set of patterns or the second set of patterns;
determining whether the new pattern is capable of being manufactured; and
updating the first set of patterns or the second set of patterns to include the new pattern based on the determination.

### Claim 4 (depends on 3)

The computer-implemented method of claim 3, further comprising:
re-training the machine learning model with the updated first set of patterns or the updated second set of patterns; and
re-generating, by the re-trained machine learning model, a new prediction model.

### Claim 5 (depends on 1)

The computer-implemented method of claim 1, wherein the second set of pixel patterns includes defect hotspots.

### Claim 6 (depends on 1)

The computer-implemented method of claim 1, wherein the design violations are determined using image processing of the IC layout, the first set of pixel patterns, and the second set of pixel patterns.

### Claim 7 (depends on 1)

The computer-implemented method of claim 1, wherein the IC layout was previously evaluated using design rule check (DRC) code.

### Claim 8

A computer-implemented method comprising:
receiving, by a prediction model, data comprising a set of test patterns comprising scanning electron microscope (SEM) images of integrated circuit (IC) patterns;
determining, by the prediction model, design violations associated with an IC layout based on the SEM images and the plurality of IC patterns by:
generating a compilation of pixel patterns including a first set of pixel patterns capable of being manufactured and a second set of pixel patterns incapable of being manufactured; and
identifying differences between the IC layout with the first set of pixel patterns and the second set of pixel patterns, wherein the design violations comprise the differences; and
providing a summary of the design violations for further characterization of the IC layout.

### Claim 9 (depends on 8)

The computer-implemented method of claim 8, wherein the design violations are further determined by:
receiving the IC layout for validation.

### Claim 10 (depends on 8)

The computer-implemented method of claim 8, wherein:
the machine learning model determines a confidence score associated with the determination of design violations;
a new pattern not belonging to the first set of patterns or the second set of patterns is identified based on the confidence score being below a threshold;
whether the new pattern is capable of being manufactured is determined; and
the first set of patterns or the second set of patterns is updated to include the new pattern based on the determination.

### Claim 11 (depends on 10)

The computer-implemented method of claim 10, wherein
the machine learning model is re-trained with the updated first set of patterns or the updated second set of patterns; and
the re-trained machine learning model re-generates a new prediction model.

### Claim 12 (depends on 8)

The computer-implemented method of claim 8, wherein the second set of pixel patterns includes defect hotspots.

### Claim 13 (depends on 8)

The computer-implemented method of claim 8, wherein the design violations are determined using image processing of the IC layout, the first set of pixel patterns, and the second set of pixel patterns.

### Claim 14 (depends on 8)

The computer-implemented method of claim 8, wherein the IC layout was previously evaluated using design rule check (DRC) code.

### Claim 15

A computer-implemented method comprising:
generating, by the machine learning model, a prediction model for validating IC layouts, wherein the prediction model is used to determine design violations associated with an IC layout based on a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns and the plurality of IC patterns, wherein the design violations are determined by:
a compilation of pixel patterns generated by the prediction model, the compilation including a first set of pixel patterns capable of being manufactured and a second set of pixel patterns incapable of being manufactured; and
differences between the IC layout with the first set of pixel patterns and the second set of pixel patterns are identified, wherein the design violations comprise the differences.

### Claim 16 (depends on 15)

The computer-implemented method of claim 15, further comprising:
determining, by the machine learning model, a confidence score associated with the determination of design violations;
identifying, based on the confidence score being below a threshold, a new pattern not belonging to the first set of patterns or the second set of patterns;
determining whether the new pattern is capable of being manufactured; and
updating the first set of patterns or the second set of patterns to include the new pattern based on the determination.

### Claim 17 (depends on 16)

The computer-implemented method of claim 16, further comprising:
re-training the machine learning model with the updated first set of patterns or the updated second set of patterns; and
re-generating, by the re-trained machine learning model, a new prediction model.

### Claim 18 (depends on 15)

The computer-implemented method of claim 15, wherein the second set of pixel patterns includes defect hotspots.

### Claim 19 (depends on 15)

The computer-implemented method of claim 15, wherein the design violations are determined using image processing of the IC layout, the first set of pixel patterns, and the second set of pixel patterns.

### Claim 20 (depends on 15)

The computer-implemented method of claim 15, wherein the design violations associated with the IC layout are further determined by using design rule check (DRC) code comprising a plurality of rules defining layout geometry for the plurality of IC patterns.