# US 2021/0240905 A1 · Advanced cell-aware fault model for yield analysis and physical failure analysis > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240905 A1 - Document ID: US20210240905A1 - Status: Published application - Kind: A1 - Application number: 17/159,017 - Filed: 2021-01-26 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: Synopsys, Inc. - Applicants: Synopsys, Inc. - Inventors: Ruifeng Guo; Brian Archer - Web page: https://patentgrep.com/patent/US20210240905A1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/3308: using simulation - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 2119/22: Yield analysis or yield optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract To specifically identify faults within a semiconductor cell, a SPICE netlist associated with the semiconductor cell design is retrieved, and one or more transistor characteristics are identified within the SPICE netlist. An advanced cell-aware fault model is executed for the semiconductor cell, and results are returned for one or more fault test methods of the advanced cell-aware fault model for a cell of the semiconductor chip design. A method for identifying faults within the semiconductor cell continues by correlating one more faults detected as a result of the fault test methods with one or more transistor characteristics within the SPICE netlist, and a user interface is generated for identifying one or more faulty transistors within the semiconductor chip design. ## Claims ### Claim 1 A method comprising: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design; receiving results of one or more fault test models for a cell of the semiconductor chip design generated at one or more output pins of the cell of the semiconductor chip design based at least in part on inputs provided to input pins of the cell of the semiconductor chip design specified by the one or more fault test models and wherein the one or more fault test models are executed based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design; correlating one or more faults detected with one or more transistor characteristics within the netlist based at least in part on the results of the one or more fault test models to identify one or more faulty transistors within the semiconductor chip design; and providing, by a processor, a user interface identifying the one or more faulty transistors within the semiconductor chip design. ### Claim 2 (depends on 1) The method of claim 1, wherein identifying one or more transistor characteristics comprises: receiving user input of transistor characteristics of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. ### Claim 3 (depends on 1) The method of claim 1, wherein providing a user interface comprises providing data identifying a location of one or more faults within the cell of the semiconductor chip design within a graphical display overlaying the location of the one or more faults onto a cell layout. ### Claim 4 (depends on 1) The method of claim 1, further comprising: generating at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics for the at least one transistor identified within the netlist wherein the user interface uniquely identifying the at least one transistor comprises data uniquely identifying the at least one transistor extracted from the netlist and data identifying the one or more transistor characteristics extracted from the netlist. ### Claim 5 (depends on 1) The method of claim 1, wherein correlating one or more faults detected with one or more transistor characteristics within the netlist comprises looking up a result generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying the expected output of the cell of the semiconductor chip design. ### Claim 6 (depends on 1) The method of claim 1, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises: identifying a library cell within the semiconductor chip design; and retrieving one or more transistor characteristics for the library cell from a memory storage area. ### Claim 7 (depends on 1) The method of claim 1, further comprising: comparing one or more transistor characteristics of the one or more faulty transistors with one or more transistor characteristics extracted from the netlist associated with the semiconductor chip design for other transistors; determining whether one or more of the transistor characteristics of the one or more faulty transistors match one or more of the transistor characteristics for at least one of the other transistors; determining whether one or more faults detected for the one or more faulty transistors are shared with the at least one of the other transistors upon determining that at least one of the transistor characteristics of the one or more faulty transistors match at least one of the transistor characteristics for the at least one of the other transistors; and upon determining at least one of the one or more faults are shared with at least one of the other transistors, identifying the at least one of the other transistors as a faulty transistor within the user interface. ### Claim 8 A system comprising: a memory storing instructions; and a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to: identify one or more transistor characteristics within a netlist associated with a semiconductor chip design; execute an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of a cell of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design and wherein providing the inputs to input pins of the cell causes the cell to generate results at one or more output pins of the cell; correlate one or more faults detected with one or more transistor characteristics within the netlist based at least in part on the results of the one or more fault test models to identify one or more faulty transistors within the semiconductor chip design; and provide a user interface identifying the one or more faulty transistors within the semiconductor chip design. ### Claim 9 (depends on 8) The system of claim 8, wherein identifying one or more transistor characteristics comprises: receiving user input of transistor characteristics of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. ### Claim 10 (depends on 8) The system of claim 8, wherein providing a user interface comprises providing data identifying a location of one or more faults within the cell of the semiconductor chip design within a graphical display overlaying the location of the one or more faults onto a cell layout. ### Claim 11 (depends on 8) The system of claim 8, wherein the processor is further configured to generate at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics for the at least one transistor identified within the netlist wherein the user interface uniquely identifying the at least one transistor comprises data uniquely identifying the at least one transistor extracted from the netlist and data identifying the one or more transistor characteristics extracted from the netlist. ### Claim 12 (depends on 8) The system of claim 8, wherein correlating one or more faults detected with one or more transistor characteristics within the netlist comprises looking up a result generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying the expected output of the cell of the semiconductor chip design. ### Claim 13 (depends on 8) The system of claim 8, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises: identifying a library cell within the semiconductor chip design; and retrieving one or more transistor characteristics for the library cell from a memory storage area. ### Claim 14 (depends on 8) The system of claim 8, wherein the processor is further configured to determine whether one or more faults detected for a semiconductor chip design are shared with a plurality of transistors within the semiconductor chip design. ### Claim 15 A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to: identify one or more transistor characteristics within a netlist associated with a semiconductor chip design; execute an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of a cell of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design and wherein providing the inputs to input pins of the cell causes the cell to generate results at one or more output pins of the cell; correlate one or more faults detected with one or more transistor characteristics within the netlist based at least in part on the results of the one or more fault test models to identify one or more faulty transistors within the semiconductor chip design; and provide a user interface identifying the one or more faulty transistors within the semiconductor chip design. ### Claim 16 (depends on 15) The non-transitory computer readable medium of claim 15, wherein identifying one or more transistor characteristics comprises: receiving user input of transistor characteristics of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. ### Claim 17 (depends on 15) The non-transitory computer readable medium of claim 15, wherein providing a user interface comprises providing data identifying a location of one or more faults within the cell of the semiconductor chip design within a graphical display overlaying the location of the one or more faults onto a cell layout. ### Claim 18 (depends on 15) The non-transitory computer readable medium of claim 15, further comprising stored instructions, which when executed by a processor, cause the processor to generate at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics for the at least one transistor identified within the netlist wherein the user interface uniquely identifying the at least one transistor comprises data uniquely identifying the at least one transistor extracted from the netlist and data identifying the one or more transistor characteristics extracted from the netlist. ### Claim 19 (depends on 15) The non-transitory computer readable medium of claim 15, wherein correlating one or more faults detected with one or more transistor characteristics within the netlist comprises looking up a result generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying the expected output of the cell of the semiconductor chip design. ### Claim 20 (depends on 15) The non-transitory computer readable medium of claim 15, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises: identifying a library cell within the semiconductor chip design; and retrieving one or more transistor characteristics for the library cell from a memory storage area.