# US 2021/0240903 A1 · Metal cut region location system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240903 A1 - Document ID: US20210240903A1 - Status: Published application - Kind: A1 - Application number: 17/237,484 - Filed: 2021-04-22 - Published: 2021-08-05 - Earliest claimed: 2018-09-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Jung-Chan YANG; Ting Yu CHEN; Li-Chun TIEN; Fong-Yuan CHANG - Web page: https://patentgrep.com/patent/US20210240903A1 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An IC layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks, position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks, overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern, and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region. ## Claims ### Claim 1 An integrated circuit (IC) layout diagram generation system comprising: a processor; and a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to: align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks; position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks; overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern; and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region. ### Claim 2 (depends on 1) The IC layout diagram generation system of claim 1, wherein the predetermined location relative to the plurality of second metal layer tracks corresponds to the border segment of the cell being aligned with a second metal layer track of the plurality of second metal layer tracks. ### Claim 3 (depends on 1) The IC layout diagram generation system of claim 1, wherein the first metal layer cut region alignment pattern has a pitch equal to a height of the cell. ### Claim 4 (depends on 1) The IC layout diagram generation system of claim 1, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: overlap a portion of the IC layout diagram external to the cell and adjacent to the border segment with another first metal layer cut region based on the first metal layer cut region alignment pattern; and extend a first metal layer region of the cell to the border segment at the portion of the IC layout diagram. ### Claim 5 (depends on 1) The IC layout diagram generation system of claim 1, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to overlap the cell with the first metal layer cut region by: overlapping a first metal layer region of the cell adjacent to a metal zero via region, wherein a distance between the first metal layer cut region and the metal zero via region has a value less than a value of a minimum metal zero via enclosure rule. ### Claim 6 (depends on 1) The IC layout diagram generation system of claim 1, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: add an extended portion to a first metal layer region of the cell; and perform an automated placement and routing (APR) operation whereby an electrical connection to the cell includes a second metal layer region overlapping the extended portion and aligned with a second metal layer track of the plurality of second metal layer tracks. ### Claim 7 (depends on 1) The IC layout diagram generation system of claim 1, wherein the first metal layer cut region alignment pattern comprises: a first sub-pattern corresponding to a first mask set; and a second sub-pattern corresponding to a second mask set. ### Claim 8 An integrated circuit (IC) layout diagram generation system comprising: a processor; and a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to: receive a cell from a cell library, the cell being free from including a first metal layer cut region; align a border segment of the cell at a predetermined location between adjacent second metal layer tracks; position the cell relative to a first metal layer cut region alignment pattern based on the second metal layer tracks; overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern; and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region. ### Claim 9 (depends on 8) The IC layout diagram generation system of claim 8, wherein the second metal layer tracks have a second metal layer pitch, and the cell has a cell height equal to a multiple of the second metal layer pitch. ### Claim 10 (depends on 8) The IC layout diagram generation system of claim 8, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: extend a first metal layer region of the cell with an extended portion reaching the border segment; and include the extended portion in a definition of an electrical connection to a first metal layer segment defined by the first metal layer region. ### Claim 11 (depends on 8) The layout diagram generation system of claim 8, wherein the border segment is a first border segment of the cell, the first metal layer cut region is a first first metal layer cut region, the first metal layer cut region alignment pattern comprises first and second sub-patterns, and the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: overlap a first portion of the IC layout diagram external to the cell and adjacent to the first border segment with a second first metal layer cut region based on the first sub-pattern; and overlap a second portion of the IC layout diagram external to the cell and adjacent to a second border segment of the cell with a third first metal layer cut region based on the second sub-pattern. ### Claim 12 (depends on 11) The layout diagram generation system of claim 11, wherein the first sub-pattern comprises a first alignment location corresponding to the first border segment, a second alignment location offset from the first alignment location by a first distance, and a third alignment location corresponding to the second border segment, and the second sub-pattern comprises a fourth alignment location corresponding to the second border segment, a fifth alignment location offset from the first alignment location by the first distance, and a sixth alignment location corresponding to the first border segment. ### Claim 13 (depends on 11) The layout diagram generation system of claim 11, wherein the first sub-pattern corresponds to a first mask set and the second sub-pattern corresponds to a second mask set. ### Claim 14 (depends on 8) The IC layout diagram generation system of claim 8, wherein the cell is a first cell, and the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: receive a second cell from the cell library, the second cell being free from including a first metal layer cut region; and position the second cell abutting the first cell and relative to the first metal layer cut region alignment pattern based on the second metal layer tracks. ### Claim 15 An integrated circuit (IC) layout diagram generation system comprising: a processor; and a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to: receive first and second cells from a cell library; align a first border segment of the first cell with a first track of a plurality of tracks corresponding to a second metal layer; align a second border segment of the first cell and a first border segment of the second cell with a second track of the plurality of tracks; align a second border segment of the second cell with a third track of the plurality of tracks; position the first and second cells relative to a first metal layer cut region alignment pattern based on the plurality of tracks; overlap at least one of the first or second cells with a first metal layer cut region based on the first metal layer cut region alignment pattern; and generate an IC layout diagram of an IC device based on the first and second cells and the first metal layer cut region. ### Claim 16 (depends on 15) The IC layout diagram generation system of claim 15, wherein the first metal layer cut region alignment pattern has a pitch equal to a distance between the first and third tracks of the plurality of tracks. ### Claim 17 (depends on 15) The IC layout diagram generation system of claim 15, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: overlap the at least one of the first or second cells with the first metal layer cut region by overlapping both of the first and second cells with the first metal layer cut region aligned along the second track of the plurality of tracks. ### Claim 18 (depends on 15) The IC layout diagram generation system of claim 15, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: connect a first metal layer region of the first cell with a corresponding first metal layer region of the second cell. ### Claim 19 (depends on 18) The IC layout diagram generation system of claim 18, wherein the non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, further cause the system to: overlap the connected first metal layer regions of the first and second cells with a first metal layer via region at a position along the second track of the plurality of tracks. ### Claim 20 (depends on 15) The layout diagram generation system of claim 15, wherein the first metal layer cut region alignment pattern comprises a first sub-pattern corresponding to a first mask set and a second sub-pattern corresponding to a second mask set, each of the first and second sub-patterns comprises a first alignment location corresponding to the first track of the plurality of tracks and a second alignment location corresponding to the third track of the plurality of tracks, and one of the first or second sub-patterns comprises a third alignment location corresponding to the second track of the plurality of tracks.