# US 2021/0240902 A1 · Integrated circuit and method of forming the same

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- Number: US 2021/0240902 A1
- Document ID: US20210240902A1
- Status: Published application
- Kind: A1
- Application number: 17/095,149
- Filed: 2020-11-11
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Yao KU; Wen-Hao CHEN; Kuan-Ting CHEN; Ming-Tao YU; Jyun-Hao CHUNG
- Web page: https://patentgrep.com/patent/US20210240902A1

## CPC

- H10D 89/10: Integrated device layouts
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10K 30/83: comprising arrangements for extracting the current from the cell, e.g. metal finger grid systems to reduce the serial resistance of transparent electrodes
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/688: {Flexible insulating substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 84/975: {Wiring regions or routing}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

## Claims

### Claim 1

A method of forming an integrated circuit, the method comprising:
generating, by a processor, a first standard cell layout design of the integrated circuit, the generating the first standard cell layout design includes:
generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width in a second direction different from the first direction, and the first standard cell layout design having a first height in the second direction;
generating a second standard cell layout design of the integrated circuit, the generating the second standard cell layout design includes:
generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width in the second direction different from the first width, and the second standard cell layout design having a second height in the second direction different from the first height, and the second standard cell layout design being adjacent to the first standard cell layout design; and
manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design.

### Claim 2 (depends on 1)

The method of claim 1, wherein
each pin layout pattern of the first set of pin layout patterns is separated from an adjacent pin layout pattern of the first set of pin layout patterns in the second direction by a first pitch; and
each pin layout pattern of the second set of pin layout patterns is separated from an adjacent pin layout pattern of the second set of pin layout patterns in the second direction by a second pitch different from the first pitch.

### Claim 3 (depends on 1)

The method of claim 1, wherein
the generating the first standard cell layout design of the integrated circuit, further includes:
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of via layout patterns having a first size, and being placed on the first set of pin layout patterns; and
the generating the second standard cell layout design of the integrated circuit, further includes:
generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of pin layout patterns having a second size different from the first size, and being placed on the second set of pin layout patterns.

### Claim 4 (depends on 3)

The method of claim 3, wherein
the first size includes at least a first via pattern width or a first via pattern height; and
the second size includes at least a second via pattern width different from the first via pattern width, or a second via pattern height different from the first via pattern height.

### Claim 5 (depends on 1)

The method of claim 1, wherein
the generating the first standard cell layout design of the integrated circuit, further includes:
generating a first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures, the first set of conductive feature layout patterns extending in the second direction, overlapping at least the first set of pin layout patterns, and being on a second layout level different from the first layout level; and
the generating the second standard cell layout design of the integrated circuit, further includes:
generating a second set of conductive feature layout patterns corresponding to fabricating a second set of conductive structures, the second set of conductive feature layout patterns extending in the second direction, overlapping at least the second set of pin layout patterns, and being on the second layout level.

### Claim 6 (depends on 5)

The method of claim 5, wherein
the generating the first standard cell layout design of the integrated circuit, further includes:
generating a third set of conductive feature layout patterns corresponding to fabricating a third set of conductive structures, the third set of conductive feature layout patterns extending in the first direction, overlapping at least the first set of conductive feature layout patterns, and being on a third layout level different from the first layout level and the second layout level; and
the generating the second standard cell layout design of the integrated circuit, further includes:
generating a fourth set of conductive feature layout patterns corresponding to fabricating a fourth set of conductive structures, the fourth set of conductive feature layout patterns extending in the first direction, overlapping at least the second set of conductive feature layout patterns, and being on the third layout level.

### Claim 7 (depends on 6)

The method of claim 6, wherein
the generating the first standard cell layout design of the integrated circuit, further includes:
generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of via layout patterns having a first size, and being placed between the first set of conductive feature layout patterns and the third set of conductive feature layout patterns; and
the generating the second standard cell layout design of the integrated circuit, further includes:
generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of via layout patterns having a second size, and being placed between the second set of conductive feature layout patterns and the fourth set of conductive feature layout patterns.

### Claim 8 (depends on 7)

The method of claim 7, wherein
the first size includes at least a first via pattern width or a first via pattern height; and
the second size includes at least a second via pattern width different from the first via pattern width, or a second via pattern height different from the first via pattern height.

### Claim 9 (depends on 6)

The method of claim 6, wherein
each conductive feature layout pattern of the third set of conductive feature layout patterns is separated from an adjacent conductive feature layout pattern of the third set of conductive feature layout patterns in the second direction by a first pitch; and
each conductive feature layout pattern of the fourth set of conductive feature layout patterns is separated from an adjacent conductive feature layout pattern of the fourth set of conductive feature layout patterns in the second direction by a second pitch different from the first pitch.

### Claim 10 (depends on 1)

The method of claim 1, wherein
the generating the first standard cell layout design of the integrated circuit, further includes:
generating a first set of active region layout patterns corresponding to fabricating a first set of active regions, the first set of active region layout patterns having a third width in the second direction, and being placed on a second layout level different from the first layout level; and
the generating the second standard cell layout design of the integrated circuit, further includes:
generating a second set of active region layout patterns corresponding to fabricating a second set of active regions, the second set of active region layout patterns having a fourth width in the second direction different from the third width, and being placed on the second layout level.

### Claim 11

A method of forming an integrated circuit, the method comprising:
placing, by a processor, a first standard cell layout design of the integrated circuit on a layout design, the first standard cell layout design having a first height, the placing the first standard cell layout design includes:
placing a first set of pin layout patterns on a first layout level and over a first set of gridlines, the first set of pin layout patterns extending in a first direction, and having a first width in a second direction different from the first direction;
placing a second standard cell layout design of the integrated circuit adjacent to the first standard cell layout design, the second standard cell layout design having a second height different from the first height, the first height and the second height being in the second direction, the placing the second standard cell layout design includes:
placing a second set of pin layout patterns on the first layout level and over a second set of gridlines, the second set of pin layout patterns extending in the first direction, and having a second width in the second direction, the second width being different from the first width; and
manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design.

### Claim 12 (depends on 11)

The method of claim 11, wherein
the placing the first standard cell layout design of the integrated circuit, further includes:
placing a first set of conductive feature layout patterns on a second layout level different from the first layout level, the first set of conductive feature layout patterns extending in the second direction, and overlapping at least the first set of pin layout patterns, and
the placing the second standard cell layout design of the integrated circuit, further includes:
placing a second set of conductive feature layout patterns and on the second layout level, the second set of conductive feature layout patterns extending in the second direction, and overlapping at least the second set of pin layout patterns.

### Claim 13 (depends on 12)

The method of claim 12, wherein
the placing the first standard cell layout design of the integrated circuit, further includes:
placing a first set of via layout patterns between the first set of pin layout patterns and the first set of conductive feature layout patterns, the first set of via layout patterns having a first via width and a first via height; and
the placing the second standard cell layout design of the integrated circuit, further includes:
placing a second set of via layout patterns between the second set of pin layout patterns and the second set of conductive feature layout patterns, the second set of via layout patterns having a second via width different from the first via width or a second via height different from the first via height.

### Claim 14 (depends on 13)

The method of claim 13, wherein
the placing the first standard cell layout design of the integrated circuit, further includes:
placing a third set of conductive feature layout patterns on a third layout level and over a third set of gridlines, the third set of conductive feature layout patterns extending in the first direction, and overlapping at least the first set of conductive feature layout patterns, the third layout level being different from the first layout level and the second layout level, and
the placing the second standard cell layout design of the integrated circuit, further includes:
placing a fourth set of conductive feature layout patterns on the third layout level and over a fourth set of gridlines, the fourth set of conductive feature layout patterns extending in the first direction, and overlapping at least the second set of conductive feature layout patterns.

### Claim 15 (depends on 14)

The method of claim 14, wherein
each gridline of the first set of gridlines is separated from an adjacent gridline of the first set of gridlines in the second direction by a first pitch of the first set of pin layout patterns;
each gridline of the second set of gridlines is separated from an adjacent gridline of the second set of gridlines in the second direction by a second pitch of the second set of pin layout patterns, the second pitch being different from the first pitch;
each gridline of the third set of gridlines is separated from an adjacent gridline of the third set of gridlines in the second direction by a third pitch of the third set of conductive feature layout patterns; and
each gridline of the fourth set of gridlines is separated from an adjacent gridline of the fourth set of gridlines in the second direction by a fourth pitch of the fourth set of conductive feature layout patterns, the fourth pitch being different from the third pitch.

### Claim 16 (depends on 14)

The method of claim 14, wherein
the placing the first standard cell layout design of the integrated circuit, further includes:
placing a third set of via layout patterns between the third set of conductive feature layout patterns and the first set of conductive feature layout patterns, the third set of via layout patterns having a third via width and a third via height; and
the placing the second standard cell layout design of the integrated circuit, further includes:
placing a fourth set of via layout patterns between the fourth set of conductive feature layout patterns and the second set of conductive feature layout patterns, the fourth set of via layout patterns having a fourth via width different from the third via width or a fourth via height different from the third via height.

### Claim 17

An integrated circuit comprising:
a first region of the integrated circuit comprising:
a first set of active regions in a substrate, the first set of active regions extending in a first direction and having a first width in a second direction different from the first direction; and
a first set of pins extending in the first direction, being over the first set of active regions, and having a second width in the second direction,
wherein the first region has a first height in the second direction; and
a second region of the integrated circuit adjacent to the first region, the second region comprising:
a second set of active regions in the substrate, the second set of active regions extending in the first direction and having a third width in the second direction different from the first width; and
a second set of pins extending in the first direction, being over the second set of active regions, and having a fourth width in the second direction different from the second width,
wherein the second region has a second height in the second direction different from the first height, and
the first set of pins and the second set of pins are in a first metal layer of the integrated circuit.

### Claim 18 (depends on 17)

The integrated circuit of claim 17, wherein
the first region of the integrated circuit further comprises:
a first set of conductive structures extending in the second direction, and overlapping at least the first set of pins, the first set of conductive structures being on a second metal layer different from the first metal layer; and
a first set of vias between the first set of pins and the first set of conductive structures, the first set of vias having a first via width and a first via height; and
the second region of the integrated circuit further comprises:
a second set of conductive structures extending in the second direction, and overlapping at least the second set of pins, the second set of conductive structures being on the second metal layer; and
a second set of vias between the second set of pins and the second set of conductive structures, the second set of vias having a second via width different from the first via width or a second via height different from the first via height.

### Claim 19 (depends on 17)

The integrated circuit of claim 17, wherein
the first set of active regions includes a first number of fins;
the second set of active regions includes a second number of fins different from the first number of fins;
each of the first set of pins is separated from an adjacent pin of the first set of pins in the second direction by a first pitch; and
each of the second set of pins is separated from an adjacent pin of the second set of pins in the second direction by a second pitch different from the first pitch.

### Claim 20 (depends on 18)

The integrated circuit of claim 18, wherein
the first region of the integrated circuit further comprises:
a third set of conductive structures extending in the first direction, and overlapping at least the first set of conductive structures, the third set of conductive structures being on a third metal layer different from the first metal layer and the second metal layer, each of the third set of conductive structures is separated from an adjacent conductive structure of the third set of conductive structures in the second direction by a first pitch; and
a third set of vias between the first set of conductive structures and the third set of conductive structures, and the third set of vias having a third via width and a third via height; and
the second region of the integrated circuit further comprises:
a fourth set of conductive structures extending in the first direction, and overlapping at least the second set of conductive structures, the fourth set of conductive structures being on the third metal layer, each of the fourth set of conductive structures is separated from an adjacent conductive structure of the fourth set of conductive structures in the second direction by a second pitch different from the first pitch; and
a fourth set of vias between the second set of conductive structures and the fourth set of conductive structures, and the fourth set of vias having a fourth via width different from the third via width or a fourth via height different from the third via height.