# US 2021/0240897 A1 · System and method for capturing hardware emulation data

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- Number: US 2021/0240897 A1
- Document ID: US20210240897A1
- Status: Published application
- Kind: A1
- Application number: 17/163,157
- Filed: 2021-01-29
- Published: 2021-08-05
- Earliest claimed: 2020-01-31
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Beshara Elmufdi
- Web page: https://patentgrep.com/patent/US20210240897A1

## CPC

- G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
- G06F 30/3312: Timing analysis
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of storing data during verification of a circuit design by a hardware emulation system, includes, in part, receiving, once in every N emulation clock cycles, P sets of register data each set including M register bits associated with the circuit design. The M register bits of each set in P shift registers are stored during M cycles of a capture clock. The stored bits are shifted out during M*P cycles of the capture clock, where (M+1)*P is less than or equal to N.

## Claims

### Claim 1

A method of storing data during verification of a circuit design by a hardware emulation system, the method comprising:
receiving, once in every N emulation clock cycles, P sets of register data each set comprising M register bits associated with the circuit design;
storing the M register bits of each set in P shift registers during M cycles of a capture clock; and
shifting out the stored bits during M*P cycles of the capture clock, wherein (M+1)*P is less than or equal to N.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
receiving input data applied to the circuit during one or more emulation cycles; and
storing the received input data in a shift register different from the P shift registers.

### Claim 3 (depends on 2)

The method of claim 2 wherein N is equal to one.

### Claim 4 (depends on 2)

The method of claim 2 further comprising:
storing the shifted out bits in a local buffer.

### Claim 5 (depends on 2)

The method of claim 2 further comprising:
compressing the shifted out bits; and
storing the compressed bits in a local buffer.

### Claim 6 (depends on 2)

The method of claim 2 further comprising:
storing the shifted out bits in a local buffer if the shifted out bits are marked as being of interest.

### Claim 7 (depends on 4)

The method of claim 4 further comprising:
disposing the data stored in the local buffer in one or more frames; and
delivering the frames to a data storage control logic.

### Claim 8 (depends on 2)

The method of claim 2 further comprising:
computing the register data associated with cycles during which the register data are not received from the register data received during cycle N and the received input data, the computed register data being computed by a software simulation tool simulating the circuit design.

### Claim 9

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
receive, once in every N emulation clock cycles, P sets of register data each set comprising M register bits associated with the circuit design;
store the M register bits of each set in P shift registers during M cycles of a capture clock; and
shift out the stored bits during M*P cycles of the capture clock, wherein (M+1)*P is less than or equal to N.

### Claim 10 (depends on 9)

The non-transitory computer readable medium of claim 9 wherein said instructions further cause the processor to:
receive input data applied to the circuit during one or more emulation cycles; and
store the received input data in a shift register different from the P shift registers.

### Claim 11 (depends on 10)

The non-transitory computer readable medium of claim 10 wherein N is equal to one.

### Claim 12 (depends on 10)

The non-transitory computer readable medium of claim 10 wherein said instructions further cause the processor to:
store the shifted out bits in a local buffer.

### Claim 13 (depends on 10)

The non-transitory computer readable medium of claim 10 wherein said instructions further cause the processor to:
compute the register data for (N−1) emulation cycles during which the register data are not received from the register data received during cycle N and the received input data, the processor configured to compute the register data by running a software simulation tool simulating the circuit design.

### Claim 14

A circuit comprising P shift registers each configured to receive, once in every N emulation clock cycles, P sets of register data each set comprising M register bits, each of the P shift registers further configured to store the M register bits during M cycles of a capture clock and shift out the stored bits during M*P cycles of the capture clock, wherein (M+1)*P is less than or equal to N.

### Claim 15 (depends on 14)

The circuit of claim 14 further comprising a shift register, different from the P shift registers, configured to receive and store input data applied to the circuit during one or more emulation cycles.

### Claim 16 (depends on 14)

The circuit of claim 14 wherein N is equal to one.

### Claim 17 (depends on 14)

The circuit of claim 14 further comprising a local buffer configured to store the shifted out bits.

### Claim 18 (depends on 14)

The circuit of claim 14 further comprising:
one or more compression blocks configured to compress the shifted out bits; and
a local buffer configured to store the compressed bits.

### Claim 19 (depends on 14)

The circuit of claim 14 further comprising a local buffer configured to store the shifted out bits if the shifted out bits are marked as being of interest.

### Claim 20 (depends on 18)

The circuit of claim 18 further comprising:
a frame transmission block configured to convert the data stored in the local buffer to frames, and deliver the frames to a data storage control logic.