# US 2021/0240870 A1 · Cryptographic key distribution > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240870 A1 - Document ID: US20210240870A1 - Status: Published application - Kind: A1 - Application number: 17/051,760 - Filed: 2019-05-02 - Published: 2021-08-05 - Earliest claimed: 2018-05-02 - Assignees: Nordic Semiconductor ASA - Applicants: Nordic Semiconductor ASA - Inventors: Frank AUNE; Jean-Baptiste BRELOT - Web page: https://patentgrep.com/patent/US20210240870A1 ## CPC - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - G06F 21/602: {Providing cryptographic facilities or services} - G06F 21/72: in cryptographic circuits - G06F 21/74: operating in dual or compartmented mode, i.e. at least one secure mode - G06F 21/85: interconnection devices, e.g. bus-connected or in-line devices - G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) - H04L 9/0897: {involving additional devices, e.g. trusted platform module [TPM], smartcard or USB} - G06F 21/107: {License processing; Key processing} - H04L 2209/12: Details relating to cryptographic hardware or logic circuitry - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An integrated-circuit device comprises a processor, a hardware key-storage system, and a key bus. The hardware key-storage system comprises a non-volatile key storage memory, which includes a key register, for storing a cryptographic key, and an address register, for storing a destination memory address for the cryptographic key. The hardware key-storage system further comprises output logic for sending the cryptographic key over the key bus to the destination memory address, and write-once logic for preventing an address being written to the address register unless the address register is in an erased state. ## Claims ### Claim 1 An integrated-circuit device comprising: a processor; a hardware key-storage system; and a key bus, wherein the hardware key-storage system comprises: a non-volatile key storage memory comprising a key register for storing a cryptographic key and an address register for storing a destination memory address for the cryptographic key; output logic for sending the cryptographic key over the key bus to the destination memory address; and write-once logic for preventing an address being written to the address register unless the address register is in an erased state. ### Claim 2 (depends on 1) The integrated-circuit device of claim 1, comprising a cryptographic engine, connected to the key bus, wherein the cryptographic engine comprises a register input for receiving a cryptographic key over the key bus. ### Claim 3 (depends on 1) The integrated-circuit device of claim 1, wherein the processor is not connected to the key bus. ### Claim 4 (depends on 1) The integrated-circuit device of claim 1, comprising a system bus, separate from the key bus, wherein the processor and the key-storage system are both connected to the system bus, and wherein the key-storage system is configured to receive instructions from the processor over the system bus. ### Claim 5 (depends on 1) The integrated-circuit device of claim 1, having a cryptographic key stored in the key register, and a destination memory address stored in the key register, wherein the destination memory address is an address of a memory location that is never readable by the processor, or that is readable by the processor only when the processor is in a secure mode. ### Claim 6 (depends on 1) The integrated-circuit device of claim 1, comprising a memory storing software for instructing the processor to write a cryptographic key to the key register, and to write a destination memory address to the key register, wherein the destination memory address is an address of a memory location that is never readable by the processor, or that is readable by the processor only when the processor is in a secure mode. ### Claim 7 (depends on 1) The integrated-circuit device of claim 1, wherein the hardware key-storage system comprises a key storage memory, wherein the key storage memory comprises the key register and the address register, and further comprises one or more configuration registers for storing configuration data relating to the cryptographic key. ### Claim 8 (depends on 1) The integrated-circuit device of claim 1, wherein the hardware key-storage system comprises read-access logic configured to prevent the processor from reading data from the key register when the processor in a non-secure mode. ### Claim 9 (depends on 1) The integrated-circuit device of claim 1, comprising a non-volatile memory controller for the non-volatile key storage memory, the non-volatile memory controller being connected to a system bus, wherein the non-volatile memory controller comprises a key management unit, the key management unit comprising said write-once logic, wherein the key management unit is configured to intercept all write messages, on the system bus, that address the address register. ### Claim 10 (depends on 1) The integrated-circuit device of claim 1, wherein the write-once logic comprises circuitry for reading part or all of the address register and for determining whether said part or all of the address register is in an erased state. ### Claim 11 (depends on 1) The integrated-circuit device of claim 1, wherein the output logic is a bus master for the key bus and is configured to write the cryptographic key to the destination memory address using direct memory access. ### Claim 12 (depends on 1) The integrated-circuit device of claim 1, comprising erase logic configured to prevent the address register from being erased unless the key register is already in an erased state, or is erased in a common erase operation with the address register. ### Claim 13 (depends on 1) The integrated-circuit device of claim 1, comprising a plurality of key registers, for storing a plurality of respective cryptographic keys, and a plurality of respective address registers, for storing a plurality of respective destination memory addresses for the cryptographic keys, wherein the output logic is configured for sending each cryptographic key over the key bus to the respective destination memory address. ### Claim 14 (depends on 13) The integrated-circuit device of claim 13, comprising first hardware for performing a first cryptographic algorithm, and second hardware for performing a second cryptographic algorithm, the first hardware and second hardware having different respective register addresses for receiving a respective cryptographic key from the key-storage system, over the key bus. ### Claim 15 A method of operating an integrated-circuit device, the integrated-circuit device comprising: a processor; a hardware key-storage system; and a key bus, wherein the hardware key-storage system comprises a non-volatile key storage memory comprising a key register that stores a cryptographic key and an address register that stores a destination memory address for the cryptographic key, the method comprising the hardware key-storage system: receiving an instruction to write a new destination memory address to the address register; determining that the address register in not in an erased state; and in response to said determining, preventing the writing of the new destination memory address to the address register. ### Claim 16 (depends on 15) The method of claim 15, comprising the hardware key-storage system sending the cryptographic key over the key bus to the destination memory address. ### Claim 17 (depends on 16) The method of claim 16, wherein the integrated-circuit device comprises a cryptographic engine connected to the key bus, and wherein the destination memory address is an address of a register input of the cryptographic engine. ### Claim 18 (depends on 15) The method of claim 15, comprising erase logic: receiving an instruction to erase the address register; and requiring the key register be erased in a common erase operation with the address register, or determining that the key register in not in an erased state and, in response to said determining, preventing erasing of the address register. ### Claim 19 (depends on 15) The method of claim 15, comprising the hardware key-storage system receiving instructions from the processor over a system bus, wherein the system bus is separate from the key bus, and wherein the processor and the hardware key-storage system are both connected to the system bus. ### Claim 20 (depends on 15) The method of claim 15, further comprising storing a cryptographic key in the key register, and storing a destination memory address in the key register, wherein the destination memory address is an address of a memory location that is never readable by the processor, or that is readable by the processor only when the processor is in a secure mode.