# US 2021/0240866 A1 · Delay-based side-channel analysis for trojan detection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240866 A1 - Document ID: US20210240866A1 - Status: Published application - Kind: A1 - Application number: 17/085,213 - Filed: 2020-10-30 - Published: 2021-08-05 - Earliest claimed: 2020-01-28 - Assignees: University of Florida Research Foundation, Inc. - Applicants: University of Florida Research Foundation, Inc. - Inventors: PRABHAT KUMAR MISHRA; YANGDI LYU - Web page: https://patentgrep.com/patent/US20210240866A1 ## CPC - G06F 21/76: in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 21/566: {Dynamic detection, i.e. detection performed at run-time, e.g. emulation, suspicious activities} - G06F 30/3308: using simulation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure describes various embodiments of systems, apparatuses, and methods for detecting a Trojan inserted integrated circuit design using delay-based side channel analysis. In one such embodiment, an automated test generation algorithm produces test patterns that are likely to activate trigger conditions and change critical paths of an integrated circuit design. ## Claims ### Claim 1 A method of detecting a Trojan inserted integrated circuit design comprising: applying test patterns as inputs to a golden integrated circuit device; measuring a propagation delay of a critical path within the golden integrated circuit device; applying the test patterns as inputs to a test integrated circuit device; measuring a propagation delay of a critical path of the test integrated circuit device; comparing the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device; and determining the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value. ### Claim 2 (depends on 1) The method of claim 1, wherein the test patterns activate a triggering condition of a Trojan circuit that is present in the test integrated circuit device and is not present in the golden integrated circuit device. ### Claim 3 (depends on 2) The method of claim 2, wherein the critical path of the test integrated circuit device is different from the critical path of the golden integrated circuit device responsive to application of the test patterns as inputs, wherein the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value. ### Claim 4 (depends on 1) The method of claim 1, further comprising determining the test integrated circuit device to not be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device does not exceed the propagation delay of the golden integrated circuit device by the threshold value. ### Claim 5 (depends on 1) The method of claim 1, wherein the test patterns are generated using a Boolean satisfiability (SAT)-based approach. ### Claim 6 (depends on 1) The method of claim 1, wherein the test patterns activate a plurality of rare nodes within the golden integrated circuit device and the test integrated circuit device. ### Claim 7 (depends on 1) The method of claim 1, further comprising ordering the test patterns to maximize a delay deviation between the golden integrated circuit device and the Trojan inserted integrated circuit device. ### Claim 8 (depends on 7) The method of claim 7, wherein a Hamming-distance based reordering of the test patterns is performed. ### Claim 9 An apparatus for detecting a Trojan inserted integrated circuit design comprising: a computer having memory and a processor that is configured to: receive an output signal from an integrated circuit device; apply test patterns as inputs to a golden integrated circuit device; receive an output signal from the golden integrated circuit device in response to the applied test patterns; measure a propagation delay of a critical path within the golden integrated circuit device; store the propagation delay for the golden integrated circuit device in a data store; apply the test patterns as inputs to a test integrated circuit device; receive an output signal from the test integrated circuit device in response to the applied test patterns; measure a propagation delay of a critical path of the test integrated circuit device; compare the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device from the data store; and determine the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the test patterns activate a triggering condition of a Trojan circuit that is present in the test integrated circuit device and is not present in the golden integrated circuit device. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the critical path of the test integrated circuit device is different from the critical path of the golden integrated circuit device responsive to application of the test patterns as inputs, wherein the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the computer having the memory and the processor is further configured to determine the test integrated circuit device to not be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device does not exceed the propagation delay of the golden integrated circuit device by the threshold value. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the test patterns are generated using a Boolean satisfiability (SAT)-based approach. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the test patterns are configured to activate a plurality of rare nodes within the golden integrated circuit device and the test integrated circuit device. ### Claim 15 (depends on 9) The apparatus of claim 9, wherein the computer having the memory and the processor is further configured to order the test patterns to maximize a delay deviation between the golden integrated circuit device and the Trojan inserted integrated circuit device. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein a Hamming-distance based reordering of the test patterns is performed. ### Claim 17 A non-transitory computer readable storage medium having instructions stored thereon that, in response to execution by a computing device, cause the computing device to perform operations comprising: applying test patterns as inputs to a golden integrated circuit device; measuring a propagation delay of a critical path within the golden integrated circuit device; applying the test patterns as inputs to a test integrated circuit device; measuring a propagation delay of a critical path of the test integrated circuit device; comparing the propagation delay of the test integrated circuit device with the propagation delay of the golden integrated circuit device; and determining the test integrated circuit device to be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device exceeds the propagation delay of the golden integrated circuit device by a threshold value. ### Claim 18 (depends on 17) The non-transitory computer readable storage medium of claim 17, wherein the test patterns activate a triggering condition of a Trojan circuit that is present in the test integrated circuit device and is not present in the golden integrated circuit device. ### Claim 19 (depends on 17) The non-transitory computer readable storage medium of claim 17, wherein the operations further comprise ordering the test patterns of the test patterns is performed. to maximize a delay deviation between the golden integrated circuit device and the Trojan inserted integrated circuit device. ### Claim 20 (depends on 17) The non-transitory computer readable storage medium of claim 17, wherein the operations further comprise determining the test integrated circuit device to not be a Trojan inserted integrated circuit device when the propagation delay of the test integrated circuit device does not exceed the propagation delay of the golden integrated circuit device by the threshold value.