# US 2021/0240655 A1 · Source ordering in device interconnects

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- Number: US 2021/0240655 A1
- Document ID: US20210240655A1
- Status: Published application
- Kind: A1
- Application number: 17/238,156
- Filed: 2021-04-22
- Published: 2021-08-05
- Earliest claimed: 2020-11-16
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Debendra Das Sharma
- Web page: https://patentgrep.com/patent/US20210240655A1

## CPC

- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 13/1626: {by reordering requests}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/4295: {using an embedded synchronisation}
- G06F 2213/0026: PCI express
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VCO, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.

## Claims

### Claim 1

An apparatus comprising:
a port to transmit and receive data over a link; and
protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol across the link, wherein protocol stack circuitry is to:
receive a request to initiate a memory write transaction on the link;
construct a memory write request transaction layer packet (TLP) for the memory write transaction, wherein fields of the memory write request TLP indicate a non-default traffic class for the TLP, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction;
cause the memory write request TLP to be transmitted over the link; and
process a completion TLP received over the link, the completion TLP indicating a completion for the memory write request TLP.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the memory write request TLP is a Memory Write TLP, and the indication that a completion is required in response to the memory write transaction is included in two upper bits of a tag field of the Memory Write TLP, two reserved bits of the Memory Write TLP, or a combination of 1 tag field bit and 1 reserved bit of the Memory Write TLP.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the memory write request TLP is a Streamed Write TLP, and the indication that a completion is required in response to the memory write transaction is included in one or more fields of the Streamed Write TLP.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the Streamed Write TLP is indicated with a value other than 0100_0000b.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the Streamed Write TLP is indicated with a value of 0101_1100b or 0101_1101b.

### Claim 6 (depends on 3)

The apparatus of claim 3, wherein the protocol stack circuitry is to construct a plurality of Streamed Write TLPs associated with the same stream identifier, the completion TLP is a Streamed Write Completion TLP that indicates a completion for each the plurality of Streamed Write TLPs.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the Streamed Write Completion TLP is indicated with a value other than 0000_1010b or 0100_1010b.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the Streamed Write Completion TLP is indicated with a value of 0000_1100b.

### Claim 9 (depends on 6)

The apparatus of claim 6, wherein a tag field of the completion TLP indicates the stream identifier associated with the plurality of Streamed Write TLPs.

### Claim 10 (depends on 6)

The apparatus of claim 6, wherein a byte count field of the completion TLP indicates a number of completions indicated by the completion TLP.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the stream identifier is indicated in a tag field of the memory write request TLP.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the memory write request TLP further includes a field indicating that completion coalescence is allowed.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the memory write request TLP is tracked using a non-posted transaction type buffer.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the protocol stack circuitry implements a PCIe-based or a CXL-based protocol across the link and the non-default traffic class indicates a virtual channel (VC) other than VC0.

### Claim 15

A method comprising:
receiving a request to initiate a memory write transaction on a link implementing a load-store input/output (I/O)-based protocol;
constructing a memory write request transaction layer packet (TLP) for the memory write transaction, wherein fields of the memory write request TLP indicate a non-default traffic class for the TLP, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction;
transmitting the memory write request TLP over the link; and
receiving a completion TLP over the link, the completion TLP indicating a completion for the memory write request TLP.

### Claim 16 (depends on 15)

The method of claim 15, wherein the memory write request TLP is a Memory Write TLP, and the indication that a completion is required in response to the memory write transaction is included in two upper bits of a tag field of the Memory Write TLP, two reserved bits of the Memory Write TLP, or a combination of 1 tag field bit and 1 reserved bit of the Memory Write TLP.

### Claim 17 (depends on 15)

The method of claim 15, wherein the memory write request TLP is a Streamed Write TLP, and the indication that a completion is required in response to the memory write transaction is included in one or more fields of the Streamed Write TLP.

### Claim 18 (depends on 17)

The method of claim 17, wherein the protocol stack circuitry is to construct a plurality of Streamed Write TLPs associated with the same stream identifier, the completion TLP is a Streamed Write Completion TLP that indicates a completion for each the plurality of Streamed Write TLPs.

### Claim 19 (depends on 18)

The method of claim 18, wherein a tag field of the completion TLP indicates the stream identifier associated with the plurality of Streamed Write TLPs.

### Claim 20 (depends on 18)

The method of claim 18, wherein a byte count field of the completion TLP indicates a number of completions indicated by the completion TLP.

### Claim 21 (depends on 15)

The method of claim 15, wherein the stream identifier is indicated in a tag field of the memory write request TLP.

### Claim 22 (depends on 15)

The method of claim 15, wherein the load-store input/output (I/O)-based protocol is a PCIe-based or a CXL-based protocol and the non-default traffic class indicates a virtual channel (VC) other than VC0.

### Claim 23

A system comprising:
a processor;
a first device; and
a second device;
wherein the processor, first device, and second device are coupled to one another via a load-store input/output (I/O) protocol-based interconnect, and each includes protocol circuitry to:
construct memory write request transaction layer packets (TLPs) for memory write transactions to be performed on the interconnect, wherein fields of the memory write request TLPs indicate a non-default traffic class for the TLP, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction; and
process completion TLPs received over the interconnect indicating completions for the memory write request TLPs.

### Claim 24 (depends on 23)

The system of claim 23, wherein the processor is a root port of the PCIe-based interconnect, the non-default traffic class indicates a virtual channel (VC) other than VC0, and the system further comprises a switch positioned in the interconnect between the processor, the first device, and the second device, wherein the switch is to transmit memory write request TLPs from the first device to the second device without involving the processor.

### Claim 25 (depends on 23)

The system of claim 23, further comprising a CXL-based switch positioned in the interconnect between the processor, the first device, and the second device, wherein the switch is to transmit memory write request TLPs from the first device to the second device using a CXL.io protocol.