# US 2021/0240653 A1 · Docks for external graphical processor units

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- Number: US 2021/0240653 A1
- Document ID: US20210240653A1
- Status: Published application
- Kind: A1
- Application number: 17/049,055
- Filed: 2018-07-16
- Published: 2021-08-05
- Earliest claimed: 2018-07-16
- Assignees: Hewlett-Packard Development Company, L.P.
- Applicants: Hewlett-Packard Development Company, L.P.
- Inventors: Roger D. Benson; Ho-sup Chung
- Web page: https://patentgrep.com/patent/US20210240653A1

## CPC

- G06F 3/1438: {using more than one graphics controller}
- G06F 13/4068: {Electrical coupling}
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 2213/0026: PCI express
- G09G 2360/06: Use of more than one graphics processor to process data before displaying to one or more screens
- G09G 2360/08: Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
- G09G 2370/12: Use of DVI or HDMI protocol in interfaces along the display data pipeline
- G09G 2370/22: Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

In example implementations, an apparatus is provided. The apparatus includes a first interface, an upstream device detector, a second interface, and a processor. The first interface receives a multi-channel connection. The upstream device detector is to detect a connection to external graphical processor unit (eGPU) via the first interface. The second interface is to connect a peripheral device that transmit data over the multi-channel connection via the first interface through the eGPU and to a host computer. The processor disables a portion of the multi-channel connection on the first interface when the upstream device detector detects the connection to the eGPU.

## Claims

### Claim 1

An apparatus, comprising:
a first interface to receive a multi-channel connection;
an upstream device detector to detect a connection to an external graphical processor unit (eGPU) via the first interface;
a second interface to connect a peripheral device that transmits data over the multi-channel connection via the first interface through the eGPU and to a host computer; and
a processor to disable a portion of the multi-channel connection on the first interface when the upstream device detector detects the connection to the eGPU.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first interface and the second interface comprise interfaces for a high speed multi-channel connection.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the high speed multi-channel connection comprise a display port channel and a peripheral component interconnect express channel.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the portion of the multi-channel connection that is disabled comprises the display port channel.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the upstream device detector exchanges messages with the eGPU when initially connected to the first connection interface to detect the eGPU.

### Claim 6

A method, comprising:
detecting, by a processor, an upstream connection to an external graphical processing unit (eGPU), wherein the upstream connection comprises a plurality of channels;
disabling, by the processor, a first channel of the upstream connection in response to the upstream connection to the eGPU that is detected; and
transmitting, by the processor, data from a peripheral device that is connected downstream to a host computer that is connected upstream of the eGPU via a second channel of the upstream connection.

### Claim 7 (depends on 6)

The method of claim 6, wherein the detecting comprises:
detecting, by the processor, a connection to an upstream connection interface; and
exchanging, by the processor, initialization messages to detect the eGPU.

### Claim 8 (depends on 6)

The method of claim 6, wherein the transmitting comprises:
detecting, by the processor, an available amount of bandwidth on the second channel of the upstream connection; and
transmitting, by the processor, the data at a throughput rate in accordance with the available amount of bandwidth on the second channel.

### Claim 9 (depends on 6)

The method of claim 6, wherein the first channel comprises display port channel.

### Claim 10 (depends on 6)

The method of claim 6, wherein the second channel comprises a peripheral component interconnect express channel.

### Claim 11

A non-transitory machine-readable storage medium encoded with instructions executable by a processor, the machine-readable storage medium comprising:
instructions to receive data from a downstream peripheral device;
instructions to determine that an upstream connection interface is connected to an external graphical processor unit (eGPU); and
instructions to transmit the data via a peripheral component interconnect express channel while a display port channel of the upstream connection interface is disabled.

### Claim 12 (depends on 11)

The non-transitory machine-readable storage medium of claim 11, wherein the data is transmitted through the eGPU to a host computer.

### Claim 13 (depends on 11)

The non-transitory machine-readable storage medium of claim 11, comprising:
instructions to block video data on the display port channel that is passed through the eGPU.

### Claim 14 (depends on 11)

The non-transitory machine-readable storage medium of claim 11, wherein the upstream connection interface comprises a Thunderbolt connection interface.

### Claim 15 (depends on 11)

The non-transitory machine-readable storage medium of claim 11, further comprising:
instructions to dynamically change an amount of data that is transmitted based on an available bandwidth on the peripheral component interconnect express channel.