# US 2021/0240634 A1 · Highly integrated scalable, flexible dsp megamodule architecture

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- Number: US 2021/0240634 A1
- Document ID: US20210240634A1
- Status: Published application
- Kind: A1
- Application number: 17/237,391
- Filed: 2021-04-22
- Published: 2021-08-05
- Earliest claimed: 2013-07-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Timothy D. Anderson; Joseph Zbiciak; Duc Quang Bui; Abhijeet Chachad; Kai Chirca; Naveen Bhoria; Matthew D. Pierson; Daniel Wu; Ramakrishnan Venkatasubramanian
- Web page: https://patentgrep.com/patent/US20210240634A1

## CPC

- G06F 12/1045: associated with a data cache
- G06F 7/24: Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers {sorting methods in general}(G06F7/36 takes precedence)
- G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)}
- G06F 7/487: Multiplying; Dividing {(G06F7/4833, G06F7/4836 take precedence)}
- G06F 7/4876: {Multiplying}
- G06F 7/49915: {Mantissa overflow or underflow in handling floating-point numbers}
- G06F 7/53: in parallel-parallel fashion, i.e. both operands being entered in parallel (G06F7/533 takes precedence)
- G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30014: {with variable precision}
- G06F 9/30018: {Bit or string instructions}
- G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30065: {Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}
- G06F 9/30072: {to perform conditional operations, e.g. using predicates or guards}
- G06F 9/3009: {Thread control instructions}
- G06F 9/30098: {Register arrangements}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30149: {of variable length instructions}
- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/3818: {Decoding for concurrent execution}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/3867: {using instruction pipelines}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/48: Program initiating; Program switching, e.g. by interrupt
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 12/0862: with prefetch
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- H03H 17/06: Non-recursive filters
- H03H 17/0664: {where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation}
- G06F 9/325: {for loops, e.g. loop detection or loop counter}
- G06F 9/381: {Loop buffering}
- G06F 9/3822: {Parallel decoding, e.g. parallel decode units}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- G06F 15/781: {On-chip cache; Off-chip memory}
- G06F 2212/452: Instruction code
- G06F 2212/60: Details of cache memory
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- H03H 2017/0298: {DSP implementation}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

Disclosed embodiments include an electronic device having a processor core, a memory, a register, and a data load unit to receive a plurality of data elements stored in the memory in response to an instruction. All of the data elements hare the same data size, which is specified by one or more coding bits. The data load unit includes an address generator to generate addresses corresponding to locations in the memory at which the data elements are located, and a formatting unit to format the data elements. The register is configured to store the formatted data elements, and the processor core is configured to receive the formatted data elements from the register.

## Claims

### Claim 1

An electronic device comprising:
a processor core;
a memory;
a register; and
a data load unit configured to receive a plurality of data elements stored in the memory in response to an instruction, wherein all of the plurality of data elements have a same data size, wherein the data size is specified by one or more coding bits, and wherein the data load unit includes:
an address generator to generate addresses corresponding to locations in the memory at which the data elements are located; and
a formatting unit to format the data elements;
wherein the register is configured to store the formatted data elements; and
wherein the processor core is configured to receive the formatted data elements from the register.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the formatting unit is configured to format the data elements using one of zero extension and sign extension.

### Claim 3 (depends on 1)

The electronic device of claim 1, wherein:
the one or more coding bits that specify the data type are first one or more coding bits; and
the formatting unit is configured to format the data elements using a formatting type specified by second one or more coding bits.

### Claim 4 (depends on 3)

The electronic device of claim 3, wherein the second one or more coding bits indicate one of zero extension and sign extension.

### Claim 5 (depends on 1)

The electronic device of claim 1, wherein the address generator is configured generate addresses using a starting address value indicated by the instruction.

### Claim 6 (depends on 5)

The electronic device of claim 5, wherein the register is a first register, wherein the electronic device comprises a second register to store the starting address value, and wherein the instruction indicates the starting address value by specifying the second register.

### Claim 7 (depends on 6)

The electronic device of claim 6, wherein the address generator is configured to generate an address corresponding to a location in the memory of at least one data element of the plurality of data elements by adding an offset to the starting address value.

### Claim 8 (depends on 7)

The electronic device of claim 7, wherein the offset is specified by the one or more coding bits.

### Claim 9 (depends on 7)

The electronic device of claim 7, wherein the offset is based on the data size of the plurality of data elements.

### Claim 10 (depends on 1)

The electronic device of claim 1, wherein the processor core comprises a plurality of functional units, and wherein at least one of the functional units is configured to perform an operation using at least one of the formatted data elements.

### Claim 11 (depends on 1)

The electronic device of claim 1, wherein the memory is a cache memory.

### Claim 12 (depends on 11)

The electronic device of claim 11, wherein the memory is a level two cache memory.

### Claim 13 (depends on 12)

The electronic device of claim 12, comprising a memory system that includes the level two cache memory and further includes a level one cache memory, and wherein the electronic device includes a data path between the register and the processor core that bypasses the level one cache memory.

### Claim 14 (depends on 1)

The electronic device of claim 1, wherein the one or more coding bits are indicated by the instruction.

### Claim 15 (depends on 14)

The electronic device of claim 14, wherein the register is a first register, wherein the electronic device includes a second register to store the one or more coding bits, and wherein the instruction indicates the one or more coding bits by specifying the second register.

### Claim 16 (depends on 1)

The electronic device of claim 1, wherein the processor core is a digital signal processing (DSP) core.

### Claim 17

A system comprising:
a memory controller;
a first memory coupled to the memory controller;
a processor having:
a processor core;
a second memory coupled to the memory controller;
a register; and
a data load unit configured to receive a plurality of data elements stored in the second memory in response to an instruction received from the first memory, wherein all of the plurality of data elements have a same data size, wherein the data size is specified by one or more coding bits, and wherein the data load unit includes:
an address generator to generate addresses corresponding to locations in the second memory at which the data elements are located; and
a formatting unit to format the data elements;
wherein the register is configured to store the formatted data elements; and
wherein the processor core is configured to receive the formatted data elements from the register.

### Claim 18 (depends on 17)

The system of claim 17, wherein the formatting unit is configured to format the data elements using one of zero extension and sign extension.

### Claim 19 (depends on 17)

The system of claim 17, wherein:
the one or more coding bits that specify the data type are first one or more coding bits; and
the formatting unit is configured to format the data elements using a formatting type specified by second one or more coding bits; and
the second one or more coding bits indicate one of zero extension and sign extension.

### Claim 20 (depends on 17)

The system of claim 17, wherein the address generator is configured generate addresses using a starting address value indicated by the instruction.

### Claim 21 (depends on 20)

The system of claim 20, wherein the register is a first register, wherein the electronic device comprises a second register to store the starting address value, and wherein the instruction indicates the starting address value by specifying the second register.

### Claim 22 (depends on 21)

The system of claim 21, wherein the address generator is configured to generate an address corresponding to a location in the second memory of at least one data element of the plurality of data elements by adding an offset to the starting address value.

### Claim 23 (depends on 22)

The system of claim 22, wherein the offset is specified by the one or more coding bits.

### Claim 24 (depends on 22)

The system of claim 22, wherein the offset is based on the data size of the plurality of data elements.

### Claim 25 (depends on 17)

The system of claim 17, wherein the processor includes a memory system that includes multiple levels of cache memory including at least a level one cache memory and a level two cache memory, wherein the second memory is a cache memory that is in a level higher than the level one cache memory.

### Claim 26 (depends on 17)

The system of claim 17, wherein the one or more coding bits are indicated by the instruction.

### Claim 27 (depends on 26)

The system of claim 26, wherein the register is a first register, wherein the electronic device includes a second register to store the one or more coding bits, and wherein the instruction indicates the one or more coding bits by specifying the second register.

### Claim 28 (depends on 17)

The system of claim 17, wherein the second memory is external to the processor.