# US 2021/0240633 A1 · Hybrid logical to physical caching scheme > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240633 A1 - Document ID: US20210240633A1 - Status: Published application - Kind: A1 - Application number: 17/234,062 - Filed: 2021-04-19 - Published: 2021-08-05 - Earliest claimed: 2018-12-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Carminantonio Manganelli; Yoav Weinberg; Alberto Sassara; Paolo Papa; Luigi Esposito; Giuseppe D'Eliseo; Angelo Della Monica; Massimo Iaculo - Web page: https://patentgrep.com/patent/US20210240633A1 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 2212/1016: Performance improvement - G06F 2212/1044: Space efficiency improvement - G06F 2212/466: Metadata, control data - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses. ## Claims ### Claim 1 A system comprising: a processing device configured to execute instructions stored on one or more components in the system, which instructions, when executed by the processing device cause the processing device to perform operations to: control access to a logical to physical (L2P) cache in a storage device and to a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog arranged to contain pairs of logical block addresses with physical addresses, each logical block address of a pair mapped to the physical address of the pair in a memory system; and access a page pointer table in the L2P cache, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address received from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog using a coldness index of the page pointer table to load the page pointer table. ### Claim 2 (depends on 1) The system of claim 1, wherein the operations include an association of a time interval with write operations to define a cold status for the coldness index. ### Claim 3 (depends on 1) The system of claim 1, wherein, with the L2P cache configured with multiple page pointer tables, the processing device is operable to adjust a coldness index for each page pointer table of the multiple page pointer tables of the L2P cache when a different page pointer table is accessed. ### Claim 4 (depends on 3) The system of claim 3, wherein the adjustment of the cold indexes is in response to the different page pointer table being one of the multiple page pointer tables of the L2P and being accessed for a read operation or a write operation, without adjusting the cold index of the different page pointer table being accessed. ### Claim 5 (depends on 3) The system of claim 3, wherein the adjustment of the cold indexes is in response to the different page pointer table being a page pointer table in the L2P changelog being accessed for a read operation or a write operation. ### Claim 6 (depends on 1) The system of claim 1, wherein, with the L2P cache configured with a first set of page pointer tables and the L2P changelog configured with a second set of page pointer tables, the processing device is operable to: transfer one or more page pointer tables of the first set to a non-volatile memory based on the coldness indexes of the one or more page pointer tables of the first set; and transfer one or more page pointer tables of the second set to the L2P cache from the L2P changelog based on the coldness indexes of the one or more page pointer tables of the second set. ### Claim 7 (depends on 1) The system of claim 1, wherein the processing device is operable to use both the L2P cache and the L2P changelog in write and read operations in the memory system. ### Claim 8 (depends on 1) The system of claim 1, wherein the page pointer table is loaded into the L2P cache from the L2P changelog in response to a determination that the coldness index identifies the page pointer table as having a hot status. ### Claim 9 (depends on 1) The system of claim 1, wherein the processing device is operable to adjust a hit rate on the L2P cache with respect write and read operations by configuring the L2P cache with most frequently accessed page pointer tables based on latest accesses by the host. ### Claim 10 (depends on 1) The system of claim 1, wherein the storage device is a volatile mentor device. ### Claim 11 A system comprising: a memory device; a storage device; a processing device configured to execute instructions stored on one or more components in the system, which instructions, when executed by the processing device cause the processing device to perform operations to: control access to the storage device arranged to include: a logical to physical (L2P) cache with the L2P cache divided in slots for page pointer tables, each page pointer table arranged as an array of physical addresses; and a L2P changelog with the L2P changelog being different from the L2P cache and with the L2P changelog having entries arranged as page pointer table lists, each page pointer table list containing one or more pairs of logical block addresses with physical addresses, the logical block address mapped to the physical address in the memory device; and manage L2P mapping by transferring a selected page point table out of the L2P cache based on a cold status of the selected page point table and transferring an identified page point table in the L2P changelog to the L2P cache based on a hot status of a page pointer table list associated with the identified page point table. ### Claim 12 (depends on 11) The system of claim 11, wherein the hot status that initiates the transfer of the identified page point table is an arrival of a pair element for the page pointer table list after the page pointer table list has been filled to a maximum number of pair elements. ### Claim 13 (depends on 12) The system of claim 12, wherein the processing device is operable to: transfer the selected page point table out of the L2P cache by loading the selected page point table to a non-volatile memory device; and remove the page pointer table list, associated with the identified page point table, from the L2P changelog. ### Claim 14 (depends on 11) The system of claim 11, wherein the processing device is operable to manage L2P mapping by identifying one or more page pointer tables in the L2P cache to be in a coldest status with respect to a total number of page pointer tables in the L2P cache and loading the identified one or more page pointers to a non-volatile memory device from the storage device. ### Claim 15 (depends on 11) The system of claim 11, wherein the processing device is operable, in a write operation, to update a target page pointer table in the L2P cache with new address information of data of the write operation. ### Claim 16 A method comprising: controlling access to a logical to physical (L2P) cache in a storage device and access to a L2P changelog in the storage device with the L2P cache being different from the L2P changelog, the L2P changelog containing pairs of logical block addresses with physical addresses, each logical block address of a pair mapped to the physical address of the pair in a memory system; and accessing a page pointer table in the L2P cache, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address received from a host, the access based on the page pointer table loaded into the L2P cache from the L2P changelog using a coldness index of the page pointer table to load the page pointer table. ### Claim 17 (depends on 16) The method of claim 16, wherein the method includes arranging the L2P changelog as a clustering of page pointer tables, with each page pointer table having one or more pairs of logical block addresses and a physical addresses. ### Claim 18 (depends on 16) The method of claim 16, wherein the method includes a processing device operating to select access to the L2P cache or the L2P changelog in write and read operations, with respect to a host, to adjust a hit rate on the L2P cache. ### Claim 19 (depends on 16) The method of claim 16, wherein the method includes, with the L2P cache configured with multiple page pointer tables, adjusting a coldness index for each page pointer table of the multiple page pointer tables of the L2P cache when a page pointer table in the L2P changelog is accessed for a read operation or a write operation or when a different page pointer table in the L2P cache is accessed for a read operation or a write operation, without adjusting the coldness index of the different page pointer table in the L2P cache. ### Claim 20 (depends on 16) The method of claim 16, wherein the method includes: loading a specific page pointer table from a memory device of the memory system into the L2P cache, in response to an element received for inclusion in a page pointer table list in the L2P changelog for the specific page pointer table with the page pointer table list filled with a maximum number of elements for the specific page pointer table prior to receiving the element; updating the specific page pointer table in the L2P cache; and freeing the page pointer table list for the specific page pointer table from a pool of lists of the page pointer tables in the L2P changelog.