# US 2021/0240632 A1 · Memory controller and operating method thereof

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- Number: US 2021/0240632 A1
- Document ID: US20210240632A1
- Status: Published application
- Kind: A1
- Application number: 16/930,863
- Filed: 2020-07-16
- Published: 2021-08-05
- Earliest claimed: 2020-02-05
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Young Ho JEON
- Web page: https://patentgrep.com/patent/US20210240632A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/10: Address translation
- G06F 2212/657: Virtual address space management
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present disclosure relates to an electronic device. A memory controller stores a stream ID by changing the stream ID on the basis of the number of updates of data and the number of times garbage collection is performed. The memory controller controlling a memory device includes a flash transition layer generating a mapping relationship of first data received from a host on the basis of a first stream ID included in the first data, a stream ID controller receiving second data for updating the first data stored in the memory device on the basis of the mapping relationship generated based on the first stream ID, and determining a second stream ID to be assigned to the second data, and a request controller outputting a program command for storing the first data and third data including the second data and the second stream ID in the memory device.

## Claims

### Claim 1

A memory controller controlling a memory device, the memory controller comprising:
a flash transition layer generating a mapping relationship of first data received from a host on the basis of a first stream ID included in the first data;
a stream ID controller receiving second data for updating the first data stored in the memory device on the basis of the mapping relationship generated based on the first stream ID, and determining a second stream ID to be assigned to the second data; and
a request controller outputting a program command for storing the first data in the memory device and a program command for storing third data including the second data and the second stream ID in the memory device,
wherein the request controller determines the program command for storing the third data in the memory device on the basis of the mapping relationship generated by the flash transition layer on the basis of the second stream ID.

### Claim 2 (depends on 1)

The memory controller of claim 1,
wherein the flash transition layer maps a logical block address received together with the first data to a physical block address indicating a region where hot data is stored when the first stream ID indicates the hot data, and
wherein the flash translation layer maps the logical block address received together with the first data to a physical block address indicating a region where cold data is stored when the first stream ID indicates the cold data.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein, when the stream ID controller receives the second data, the stream ID controller outputs a stream ID request for obtaining the first stream ID to the memory device, and receives the first stream ID corresponding to the stream ID request from the memory device.

### Claim 4 (depends on 3)

The memory controller of claim 3, wherein the third data includes the second data and the second stream ID maintaining or changing a value corresponding to the first stream ID.

### Claim 5 (depends on 3)

The memory controller of claim 3, wherein the stream ID controller generates an update count by counting a number of times that a logical block address for updating the second data is received together with the second data and a garbage collection count by counting a number of times that data stored in a physical block address corresponding to the logical block address received together with the second data is moved to another memory block in the memory device.

### Claim 6 (depends on 5)

The memory controller of claim 5, wherein the stream ID controller reduces a value of the first stream ID when the update count is a first reference value or more.

### Claim 7 (depends on 6)

The memory controller of claim 6, wherein the stream ID controller maintains the value of the first stream ID when the value of the first stream ID is a minimum value among a set range of values and the update count is the first reference value or more.

### Claim 8 (depends on 5)

The memory controller of claim 5, wherein the stream ID controller increases a value of the first stream ID when the garbage collection count is a second reference value or more.

### Claim 9 (depends on 8)

The memory controller of claim 8, wherein the stream ID controller maintains the value of the first stream ID when the value of the first stream ID is a maximum value among a set range of values and the garbage collection count is the second reference value or more.

### Claim 10 (depends on 1)

The memory controller of claim 1, wherein the stream ID controller comprises:
an update counter generating an update count by counting a number of times that a logical block address of updating second data is received together with the second data;
a garbage collection counter generating a garbage collection count by counting a number of times that data stored in a physical block address corresponding to the logical block address received together with the second data is moved to another memory block in the memory device;
a stream ID changer determining the second stream ID to be assigned to the second data; and
a data generator generating the third data including the second data and the second stream ID.

### Claim 11 (depends on 10)

The memory controller of claim 10, wherein, when the stream ID controller receives the second data, the stream ID changer outputs a stream ID request for obtaining the first stream ID from the memory device, and receives the first stream ID corresponding to the stream ID request from the memory device.

### Claim 12 (depends on 11)

The memory controller of claim 11, wherein the stream ID changer reduces a value of the first stream ID when the update count is a first reference value or more, and increases the value of the first stream ID when the garbage collection count is a second reference value or more.

### Claim 13 (depends on 11)

The memory controller of claim 11, wherein the stream ID changer maintains a value corresponding to the first stream ID when a value obtained by reducing or increasing the value corresponding to the first stream ID exceeds predetermined values.

### Claim 14

A method of operating a memory controller controlling a memory device, the method comprising:
receiving first data from a host;
generating a mapping relationship of the first data on the basis of a first stream ID included in the first data;
outputting a program command for storing the first data in the memory device on the basis of the mapping relationship;
receiving second data for updating the first data from the host; and
determining a second stream ID to be assigned to the second data.

### Claim 15 (depends on 14)

The method of claim 14, wherein the determining of the second stream ID to be assigned to the second data comprises:
outputting a stream ID request for obtaining the first stream ID to the memory device; and
receiving the first stream ID corresponding to the stream ID request from the memory device.

### Claim 16 (depends on 15)

The method of claim 15, further comprising generating third data including the second data and the second stream ID maintaining or changing a value corresponding to the first stream ID.

### Claim 17 (depends on 14)

The method of claim 14, further comprising generating an update count by counting a number of times that a logical block address for updating the second data is received together with the second data and a garbage collection count by counting a number of times that data stored in a physical block address corresponding to the logical block address received together with the second data is moved to another memory block in the memory device.

### Claim 18 (depends on 17)

The method of claim 17, wherein the determining of the second stream ID to be assigned to the second data comprises reducing a value of the first stream ID when the update count is a first reference value or more.

### Claim 19 (depends on 17)

The method of claim 17, wherein the determining of the second stream ID to be assigned to the second data comprises increasing a value of the first stream ID when the garbage collection count is a second reference value or more.

### Claim 20 (depends on 17)

The method of claim 17, wherein the determining of the second stream ID to be assigned to the second data comprises maintaining a value corresponding to the first stream ID when a value obtained by reducing or increasing the value corresponding to the first stream ID exceeds predetermined values.

### Claim 21

A memory system comprising:
a memory device suitable for storing current data together with a current stream identification (ID) into a storage region corresponding to the current stream ID; and
a controller suitable for:
counting a number of times that a logical address is provided for updating the current data with updated data to generate a first number;
counting a number of times that a garbage collection operation is performed on a storage area corresponding to the logical address to generate a second number;
adjusting, in response to a request of updating the current data, a value of the current steam ID resulting in an adjusted stream ID based on the first and second numbers;
controlling the memory device to store the updated data together with the adjusted stream ID in a storage region corresponding to the adjusted stream ID; and
invalidating the current data together with the current stream ID.