# US 2021/0240631 A1 · Cache memory device, system including the same, and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240631 A1 - Document ID: US20210240631A1 - Status: Published application - Kind: A1 - Application number: 17/000,875 - Filed: 2020-08-24 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: HYUNWOOK JOO - Web page: https://patentgrep.com/patent/US20210240631A1 ## CPC - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/30101: {Special purpose registers} - G06F 12/0811: with multilevel cache hierarchies - G06F 12/0864: using pseudo-associative means, e.g. set-associative or hashing - G06F 12/0891: using clearing, invalidating or resetting means - G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning - G06F 12/1441: {for a range} - G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel - G06F 2212/1021: Hit rate improvement - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2212/6032: Way prediction in set-associative cache - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A cache memory device includes a cache circuit and a way prediction circuit. The cache circuit generates a cache hit signal indicating whether target data corresponding to an access address are stored in cache lines and performs a current cache access operation primarily with respect to candidate ways based on a candidate way signal indicating the candidate ways in a way prediction mode. The way prediction circuit stores accumulation information by accumulating a cache hit result indicating whether the target data are stored in one of ways and a way prediction hit result indicating whether the target data are stored in one of the candidate ways based on the cache hit signal provided during previous cache access operations. The way prediction circuit generates the candidate way signal by determining the candidate ways for the current cache access operation based on the accumulation information in the way prediction mode. ## Claims ### Claim 1 A cache memory device comprising: a cache circuit including a plurality ways, wherein each of the plurality of ways includes a plurality of cache lines corresponding to a plurality of sets, and the cache circuit is configured to generate a cache hit signal indicating whether target data corresponding to an access address are stored in the plurality of cache lines and configured to perform a current cache access operation with respect to candidate ways among the plurality of ways based on a candidate way signal indicating the candidate ways in a way prediction mode; and a way prediction circuit configured to store accumulation information by accumulating a cache hit result indicating whether the target data are stored in one of the plurality of ways and a way prediction hit result indicating whether the target data are stored in one of the candidate ways based on the cache hit signal provided during a plurality of previous cache access operations, and configured to generate the candidate way signal by determining the candidate ways for the current cache access operation based on the accumulation information in the way prediction mode. ### Claim 2 (depends on 1) The cache memory device of claim 1, wherein the way prediction circuit generates a prediction mode signal indicating enable or disable of the way prediction mode based on the accumulation information, and provides the prediction mode signal to the cache circuit. ### Claim 3 (depends on 2) The cache memory device of claim 2, wherein, when the prediction mode signal indicates the enable of the way prediction mode, the cache circuit perform a primary cache access operation with respect to the candidate ways, and performs a secondary cache access operation with respect to other ways except the candidate ways, among the plurality of ways, only when the target data are not stored in the candidate ways. ### Claim 4 (depends on 2) The cache memory device of claim 2, wherein, when the prediction mode signal indicates the disable of the way prediction mode, the cache circuit performs a normal cache access operation with respect to all of the plurality of ways. ### Claim 5 (depends on 1) The cache memory device of claim 1, wherein the way prediction circuit includes: an auxiliary inference buffer configured to store eviction information on evicted data that are replaced by new data and deleted from the plurality of cache lines during a valid re-reference interval. ### Claim 6 (depends on 5) The cache memory device of claim 5, wherein the way prediction circuit generates shield information on protection data based on the eviction information, and provides the shield information to the cache circuit, wherein the protection data indicates the evicted data that are written again in the cache line during the valid re-reference interval, and wherein the cache circuit prevents the protection data from being deleted from the cache line at least one time based on the shield information. ### Claim 7 (depends on 5) The cache memory device of claim 5, wherein the eviction information includes an address of the evicted data, a victim identifier indicating a processor that previously wrote the evicted data in the cache line, and an attacker identifier indicating a processor that deleted the evicted data from the cache line. ### Claim 8 (depends on 7) The cache memory device of claim 7, wherein the way prediction circuit stores cache occupation information indicating identifiers of processors corresponding to data stored in the plurality of cache lines and determines the victim identifier based on the cache occupation information. ### Claim 9 (depends on 5) The cache memory device of claim 5, wherein the valid re-reference interval is determined based on a multiplication of a number of processors that commonly access the cache circuit and a number of the plurality of ways. ### Claim 10 (depends on 1) The cache memory device of claim 1, wherein the cache memory device is a shared cache memory device that is accessed commonly by a plurality of processors. ### Claim 11 (depends on 10) The cache memory device of claim 10, wherein the way prediction circuit includes: a differential diagnosis register configured to, with respect to each of the plurality of processors and each of the plurality of sets, store the accumulation information by accumulating a plurality of diagnosis bit pairs during the plurality of previous cache access operations, wherein each diagnosis bit pair includes a cache hit bit indicating the cache hit result and a way prediction hit bit indicating the way prediction hit result; and a control logic circuit configured to generate the candidate way signal corresponding to a processor and a set related with the current cache access operation based on the plurality of diagnosis bit pairs stored in the differential diagnosis register. ### Claim 12 (depends on 11) The cache memory device of claim 11, wherein the way prediction circuit further includes: a way rank buffer configured to, with respect to each of the plurality of processors and each of the plurality of sets, store priority information indicating an order that the plurality of ways are included in the candidate ways. ### Claim 13 (depends on 12) The cache memory device of claim 12, wherein the control logic circuit updates the priority information on the fly per cache access operation based on the plurality of diagnosis bit pairs. ### Claim 14 (depends on 12) The cache memory device of claim 12, wherein the control logic circuit stores a plurality of way prediction windows corresponding to the plurality of processors and the plurality of sets, wherein each of the plurality of way prediction windows indicates a number of the candidate ways corresponding to each processor and each set, and the control logic circuit determines the candidate ways corresponding to a processor and a set related with the current cache access operation based on the plurality of way prediction windows and the priority information. ### Claim 15 (depends on 14) The cache memory device of claim 14, wherein the control logic circuit updates the plurality of way prediction windows on the fly per cache access operation based on the plurality of diagnosis bit pairs. ### Claim 16 (depends on 1) The cache memory device of claim 1, wherein the cache memory device is a private cache memory device that is accessed dedicatedly by a single processor. ### Claim 17 (depends on 16) The cache memory device of claim 16, wherein the way prediction circuit includes: a differential diagnosis register configured to, with respect to the single processor and each of the plurality of sets, store the accumulation information by accumulating a plurality of diagnosis bit pairs during the plurality of previous cache access operations, wherein each diagnosis bit pair includes a cache hit bit indicating the cache hit result and a way prediction hit bit indicating the way prediction hit result; and a control logic circuit configured to generate the candidate way signal corresponding to the single processor and a set related with the current cache access operation based on the plurality of diagnosis bit pairs stored in the differential diagnosis register. ### Claim 18 (depends on 17) The cache memory device of claim 17, wherein the way prediction circuit further includes: a way rank buffer configured to, with respect to the single processor and each of the plurality of sets, store priority information indicating an order that the plurality of ways are included in the candidate ways, and wherein the control logic circuit updates the priority information on the fly per cache access operation based on the plurality of diagnosis bit pairs. ### Claim 19 A system comprising: one or more processors; a main memory device configured to store data used by the one or more processors; and a cache memory device configured to store a portion of the data stored in the main memory device and configured to be accessed by the one or more processors before the one or more processors access the main memory device, wherein the cache memory device comprises: a cache circuit including a plurality ways, wherein each of the plurality of ways includes a plurality of cache lines corresponding to a plurality of sets, and the cache circuit is configured to generate a cache hit signal indicating whether target data corresponding to an access address are stored in the plurality of cache lines and configured to perform a current cache access operation with respect to candidate ways among the plurality of ways based on a candidate way signal indicating the candidate ways in a way prediction mode; and a way prediction circuit configured to store accumulation information by accumulating a cache hit result indicating whether the target data are stored in one of the plurality of ways and a way prediction hit result indicating whether the target data are stored in one of the candidate ways based on the cache hit signal provided during a plurality of previous cache access operations, and configured to generate the candidate way signal by determining the candidate ways for the current cache access operation based on the accumulation information in the way prediction mode. ### Claim 20 A method of operating a cache memory device including a plurality of ways, each of the plurality of ways including a plurality of cache lines corresponding to a plurality of sets, the method comprising: generating a cache hit signal indicating whether target data corresponding to an access address are stored in the plurality of cache lines; storing accumulation information by accumulating a cache hit result indicating whether the target data are stored in one of the plurality of ways and a way prediction hit result indicating whether the target data are stored in one of candidate ways based on the cache hit signal provided during a plurality of previous cache access operations; generating a candidate way signal by determining the candidate ways for a current cache access operation among the plurality of ways based on the accumulation information in a way prediction mode; and performing the current cache access operation with respect to the candidate ways based on the candidate way signal in the way prediction mode. ### Claim at position 21 21-25. (canceled)