# US 2021/0240625 A1 · Management of coherency directory cache entry ejection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240625 A1 - Document ID: US20210240625A1 - Status: Published application - Kind: A1 - Application number: 17/301,949 - Filed: 2021-04-20 - Published: 2021-08-05 - Earliest claimed: 2019-04-30 - Assignees: Hewlett Packard Enterprise Development LP - Applicants: Hewlett Packard Enterprise Development LP - Inventors: Frank R. Dropps - Web page: https://patentgrep.com/patent/US20210240625A1 ## CPC - G06F 12/0817: using directory methods - G06F 12/0822: {Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831)} - G06F 12/0813: with a network or matrix configuration - G06F 12/124: {being minimized, e.g. non MRU} - G06F 2212/1016: Performance improvement - G06F 2212/608: Details relating to cache mapping - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules. ## Claims ### Claim 1 An apparatus, comprising: one or more memory devices including: one or more trackers indicating if memory blocks are in an active state within a respective memory region of a memory; and a coherency directory cache comprising a plurality of directory cache entries, each of the directory cache entries being configured to store a copy of a directory entry from a coherency directory, and each of the directory entries being configured to include state and ownership information of a respective memory block of the memory; and one or more hardware components configured to: receive a request including a memory address of a first memory block; detect a cache hit in the coherency directory cache based on the memory address included in the request; determine that the request is to change the state of the first memory block in a respective first directory cache entry among the plurality of directory cache entries to an invalid state; and manage the ejection of the first directory cache entry from the coherency directory cache based on one or more ejection policy rules. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the policy rules include: a first ejection policy rule, wherein the first directory cache entry is optionally ejected based on requirements of a directory cache replacement algorithm; a second ejection policy rule, wherein the first directory cache entry is ejected based on one or more tracking requirements; and a third ejection policy rule, wherein the first directory cache entry is ejected independent of other requirements. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the directory cache replacement algorithm is a least recently used (LRU) algorithm wherein the first directory cache entry is ejected based on respective replacement metrics of the plurality of directory cache entries. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the replacement metrics indicate the age, ranking or position of each of the plurality of directory cache entries relative to one another based on a measure of the amount of time since each respective memory block of the plurality of directory cache entries was last accessed. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein, for the first ejection policy rule, the first directory cache entry is ejected when an uncached one of the directory entries from the coherency directory needs to be cached and none of the plurality of directory cache entries are unused. ### Claim 6 (depends on 3) The apparatus of claim 3, wherein the tracking requirements require that the first directory cache entry be in an invalid state as determined based on the trackers associated with the memory region that includes the first memory block. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the one or more policy rules for managing the ejection of the first directory cache entry is determined based on an ejection action level value associated with the first memory block. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein managing the ejection of the first directory cache entry includes ejecting the first directory cache entry, the ejecting including removing from the first directory cache entry the copy of the directory entry corresponding to the first directory cache entry. ### Claim 9 (depends on 8) The apparatus of claim 8, the one or more hardware components being configured to manage requests relating to at least the memory, the memory including one or more memory devices forming a shared memory accessible by one or more processors. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the inactive state indicates that the respective memory block is not cached in any caches of the one or more remote processors, and wherein the active state includes one or more states in which the memory block is cached in at least one cache of the one or more remote processors. ### Claim 11 A method comprising: receiving a request including a first memory address of a first memory block in a memory; detecting, based on the first memory address received in the request, a cache hit in a coherency directory cache, the cache hit indicating that a first directory cache entry of a plurality of directory cache entries in the coherency directory cache corresponds to the first memory block, and each of the plurality of directory cache entries being configured to include state and ownership information of a respective memory block in the memory; determining that the request is to change the state of the first memory block in a respective first directory cache entry to an invalid state; and managing the ejection of the first directory cache entry from the coherency directory cache based on one of or more policy rules. ### Claim 12 (depends on 11) The method of claim 11, wherein the policy rules include: a first ejection policy rule, wherein the first directory cache entry is optionally ejected based on requirements of a directory cache replacement algorithm; a second ejection policy rule, wherein the first directory cache entry is ejected based on one or more tracking requirements; and a third ejection policy rule, wherein the first directory cache entry is ejected independent of other requirements. ### Claim 13 (depends on 12) The method of claim 12, wherein the directory cache replacement algorithm is a least recently used (LRU) algorithm wherein the first directory cache entry is ejected based on respective replacement metrics of the plurality of directory cache entries, and wherein the replacement metrics indicate the age, ranking or position of each of the plurality of directory cache entries relative to one another based on a measure of the amount of time or order since each respective memory block of the plurality of directory cache entries was last accessed. ### Claim 14 (depends on 13) The method of claim 13, further comprising: storing tracking information corresponding to memory regions of the memory, the tracking information indicating if memory blocks within the respective memory region are in an active state; and adjusting the tracking information corresponding to the memory region that includes the first memory block. ### Claim 15 (depends on 14) The method of claim 14, wherein managing the ejection of the first directory cache entry includes ejecting the first directory cache entry, the ejecting including removing from the first directory cache entry the data stored therein that corresponds to a coherency directory entry of a respective coherency directory. ### Claim 16 (depends on 15) The method of claim 15, further comprising managing requests relating to at least the memory, the memory including one or more memory devices forming a shared memory accessible by one or more processors. ### Claim 17 (depends on 16) The method of claim 16, wherein the inactive state indicates that the respective memory block is not cached in any caches of the one or more remote processors, and wherein the active state includes one or more states in which the memory block is cached in at least one cache of the one or more remote processors. ### Claim 18 An apparatus comprising: a request accelerator configured to store tracking information, the tracking information indicating if memory blocks are in an active state within a respective memory region; and a coherency controller including: a coherency directory cache comprising a plurality of directory cache entries, each of the directory cache entries being configured to store a copy of a directory entry from a coherency directory, and each of the directory entries being configured to include state and ownership information of a respective memory block of the memory, wherein the coherency controller is configured to manage the ejection of used directory cache entries from the coherency directory cache based on one or more ejection policy rules, wherein the managing of the ejection of used directory cache entries includes ejecting at least one of the used directory cache entries by removing therefrom the copy of the respective directory entry. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein, for a first directory cache entry identified in a request that causes changing a state of the first directory cache to invalid, the ejection policy rules include: a first ejection policy rule, wherein the first directory cache entry is optionally ejected based on requirements of a directory cache replacement algorithm; a second ejection policy rule, wherein the first directory cache entry is ejected based on one or more tracking requirements that, in part, require that the first directory cache entry be in an invalid state as determined based tracking information associated with the memory region that includes the first memory block; and a third ejection policy rule, wherein the first directory cache entry is ejected independent of other requirements. ### Claim 20 (depends on 19) A system comprising: at least one of the apparatus of claim 19, wherein the at least one the apparatus is communicatively coupled to a plurality of processors and respective memories, each of the at least one of the apparatus being associated with a subset of the plurality of processors and respective memories forming a shared memory accessible by the plurality of processors, and each of the at least one of the apparatus manages requests relating to its associated subset of memories.