# US 2021/0240624 A1 · Cpu cache flushing to persistent memory

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- Number: US 2021/0240624 A1
- Document ID: US20210240624A1
- Status: Published application
- Kind: A1
- Application number: 17/239,454
- Filed: 2021-04-23
- Published: 2021-08-05
- Earliest claimed: 2018-02-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Paul Stonelake; Samir Mittal
- Web page: https://patentgrep.com/patent/US20210240624A1

## CPC

- G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24)
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 1/3212: Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 12/0893: Caches characterised by their organisation or structure
- G06F 2212/1052: Security improvement
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

## Claims

### Claim 1

A system comprising:
a detector configured to detect an impending loss of power from a power supply; and
at least one memory component configured to store first data associated with write commands received from a host system, wherein the write commands are sent by the host system responsive to a signal provided to the host system by a power supply monitor, and wherein the power supply monitor provides the signal responsive to detecting an impending loss of power from the power supply;
wherein responsive to detecting, by the detector, the impending loss of power, the first data is stored in the at least one memory component.

### Claim 2 (depends on 1)

The system of claim 1, wherein the write commands correspond to write operations committed to a memory controller by a processing device of the host system.

### Claim 3 (depends on 2)

The system of claim 2, wherein the write operations are committed to the memory controller by software executing on the host system, and the write commands are flushed by the software responsive to the signal provided to the host system by the power supply monitor.

### Claim 4 (depends on 3)

The system of claim 3, wherein the write commands are flushed during an asynchronous memory refresh sequence.

### Claim 5 (depends on 3)

The system of claim 3, wherein the write commands are flushed from a protected write queue.

### Claim 6 (depends on 5)

The system of claim 5, wherein the write commands in the protected write queue correspond to stores to be persisted by the host system.

### Claim 7 (depends on 6)

The system of claim 6, wherein the software ensures that stores prior to a store fence instruction are globally visible in the host system before any store after the store fence instruction becomes globally visible in the host system.

### Claim 8 (depends on 6)

The system of claim 6, wherein the software executing on the host system moves the write commands to the protected write queue prior to retiring the stores.

### Claim 9 (depends on 1)

The system of claim 1, wherein the detector detects the impending loss of power when a supply voltage obtained from the power supply falls below a predetermined threshold.

### Claim 10 (depends on 1)

The system of claim 1, wherein the power supply monitor is external to the host system.

### Claim 11 (depends on 1)

The system of claim 1, wherein the first data is stored in the memory component less than 20 ms after the host system receives the signal from the power supply monitor.

### Claim 12 (depends on 4)

The system of claim 4, wherein the write commands are moved to the protected write queue from at least one cache of a processing device of the host system.

### Claim 13 (depends on 1)

The system of claim 1, further comprising at least one capacitor configured to provide power for storing data, wherein the first data is stored in the memory component using power supplied by the at least one capacitor.

### Claim 14 (depends on 1)

The system of claim 1, further comprising a cache configured to receive the write commands.

### Claim 15 (depends on 14)

The system of claim 14, wherein the cache comprises volatile memory, and the first data is stored in non-volatile memory.

### Claim 16

A system comprising:
a cache configured to receive, via a memory interface, write commands from a host system, wherein the write commands are sent responsive to a signal provided to the host system by a power supply monitor, and wherein the power supply monitor provides the signal responsive to detecting an impending loss of power provided by a power supply;
a detector configured to detect a loss of power; and
a controller configured to, responsive to the detector detecting the loss of power:
disable the memory interface; and
store data associated with the write commands that are received by the cache prior to disabling the memory interface, wherein the data is stored in at least one memory component.

### Claim 17 (depends on 16)

The system of claim 16, further comprising at least one capacitor, wherein the data is stored using power supplied by the at least one capacitor.

### Claim 18 (depends on 17)

The system of claim 17, wherein the at least one capacitor provides at least 10 ms of holdup time.

### Claim 19 (depends on 16)

The system of claim 16, wherein the write commands are in a protected write queue and correspond to stores to be persisted by the host system, and wherein software executing on the host system moves the write commands to the protected write queue prior to retiring the stores.

### Claim 20 (depends on 19)

The system of claim 19, wherein the write commands are flushed from the protected write queue during an asynchronous memory refresh sequence.

### Claim 21 (depends on 16)

The system of claim 16, further comprising, responsive to the detector detecting the loss of power, generating a log associated with storing the data.

### Claim 22

A method comprising:
receiving, by a memory module, write commands from a host system, wherein the write commands are sent by the host system responsive to a signal provided by a power supply monitor, and wherein the power supply monitor provides the signal in response to detecting a loss of power to the host system;
detecting a loss of power to the memory module; and
responsive to detecting the loss of power to the memory module, storing data associated with the received write commands, wherein the data is stored in non-volatile memory.

### Claim 23 (depends on 22)

The method of claim 22, wherein the write commands are received over a memory interface.

### Claim 24 (depends on 23)

The method of claim 23, further comprising, in response to detecting the loss of power to the memory module, disabling the memory interface.