# US 2021/0240623 A1 · Shared buffered memory routing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240623 A1 - Document ID: US20210240623A1 - Status: Published application - Kind: A1 - Application number: 17/236,692 - Filed: 2021-04-21 - Published: 2021-08-05 - Earliest claimed: 2015-03-27 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Debendra Das Sharma; Michelle C. Jen; Brian S. Morris - Web page: https://patentgrep.com/patent/US20210240623A1 ## CPC - G06F 12/084: with a shared cache - G06F 3/061: {Improving I/O performance} - G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration} - G06F 3/0673: {Single storage device} - G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems - G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence) - G06F 13/1673: {using buffers} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 2212/1016: Performance improvement - G06F 2212/60: Details of cache memory - G06F 2212/62: Details of cache specific to multiprocessor cache arrangements - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path ## Claims ### Claim 1 An integrated circuit die comprising: a plurality of controllers, including a network controller and a shared memory controller; a processor coupled to the plurality of controllers; and a multi-lane communication interface coupled to the plurality of controllers, the multi-lane communication interface comprising an electrical sub-block to physically transmit information to an off-die device, the electrical sub-block comprising: a transmitter to transmit information to the off-die device via a first differential signal path; and a receiver to receive information from the off-die device via a second differential signal path, the transmitter and the receiver corresponding to one of a plurality of lanes of the multi-lane communication interface; wherein the multi-lane communication interface supports a first layered protocol stack and a second layer protocol stack, the first layered protocol stack and the second layered protocol stack overlaid on the electrical sub-block, wherein the electrical sub-block is switchable to transmit and receive information in accordance with the first layered protocol stack or to transmit and receive information in accordance with the second layered protocol stack. ### Claim 2 (depends on 1) The integrated circuit die of claim 1, wherein the first layered protocol stack comprises a first link layer implemented in a first link layer circuitry, and the second layered protocol stack comprises a second link layer different from the first link layer, the second link layer implemented in second link layer circuitry. ### Claim 3 (depends on 2) The integrated circuit die of claim 2, wherein the transmitter is to serialize information for transmission to the off-die device and the receiver is to deserialize information received from the off-die device. ### Claim 4 (depends on 3) The integrated circuit die of claim 3, wherein the multi-lane communication interface is a serial point-to-point link interface. ### Claim 5 (depends on 4) The integrated circuit die of claim 4, further comprising logical PHY circuitry coupled to the first link layer circuitry and the second link layer circuitry to prepare outgoing information for transmission by the electrical sub-block, the outgoing information comprising an error detection code associated with a flit. ### Claim 6 (depends on 5) The integrated circuit die of claim 5, wherein the flit is a multi-slotted flit. ### Claim 7 (depends on 6) The integrated circuit die of claim 6, wherein the error detection code is a CRC value. ### Claim 8 (depends on 7) The integrated circuit die of claim 7, wherein the error detection code is a 16-bit CRC value. ### Claim 9 (depends on 8) The integrated circuit die of claim 8, wherein the processor comprises a first processor core and a second processor core, wherein the first processor core and the second processor core are operable as independent nodes under control of a virtual machine monitor. ### Claim 10 (depends on 8) The integrated circuit die of claim 8, wherein the first protocol stack is a network protocol stack. ### Claim 11 (depends on 8) The integrated circuit die of claim 8, wherein the first protocol stack is an input/output (I/O) protocol stack. ### Claim 12 (depends on 11) The integrated circuit die of claim 11, wherein the second layered protocol stack is a memory access protocol stack. ### Claim 13 (depends on 11) The integrated circuit die of claim 11, wherein the memory access protocol stack is a coherent memory access protocol stack. ### Claim 14 (depends on 13) The integrated circuit die of claim 13, further comprising a first set of transmission paths to transmit serial data in accordance with the first layered protocol stack and a second set of transmission paths to transmit serial data in accordance with the second layered protocol stack. ### Claim 15 (depends on 14) The integrated circuit die of claim 14, wherein the first set of transmission paths and the second set of transmission paths comprise respective copper lines. ### Claim 16 An integrated circuit die comprising: a plurality of controllers, including a first shared memory controller (SMC) to be coupled to a local memory device and at least one remote memory device; a processor coupled to the plurality of controllers; and a multi-lane communication interface coupled to the plurality of controllers, the multi-lane communication interface comprising an electrical sub-block to physically transmit and receive information, the electrical sub-block comprising: a transmitter to transmit information; and a receiver to receive information, the transmitter and the receiver corresponding to one of a plurality of lanes of the multi-lane communication interface; wherein the multi-lane communication interface supports a first layered protocol stack and a second layered protocol stack, the first layered protocol stack and the second layered protocol stack overlaid on the electrical sub-block, wherein the electrical sub-block is switchable to transmit and receive information in accordance with the first layered protocol stack or to transmit and receive information in accordance with the second layered protocol stack; wherein the second layered protocol stack is a memory access protocol stack comprising an upper protocol layer to route a memory access request to the remote memory device or the local memory device. ### Claim 17 (depends on 16) The integrated circuit die of claim 16 wherein the upper protocol layer comprises a transaction layer or a link layer of the memory access protocol stack. ### Claim 18 (depends on 16) The integrated circuit die of claim 16, wherein to route a memory access request to the remote memory device, the upper protocol layer is to route the memory access request over one or more of the plurality of lanes to a second die comprising a second SMC coupled to the remote memory. ### Claim 19 (depends on 16) The integrated circuit die of claim 16 wherein the first layered protocol stack comprises a first link layer implemented in a first link layer circuitry, and the second layered protocol stack comprises a second link layer different from the first link layer, the second link layer implemented in second link layer circuitry. ### Claim 20 (depends on 19) The integrated circuit die of claim 19, wherein the transmitter is to serialize information for transmission to the off-die device and the receiver is to deserialize information received from the off-die device. ### Claim 21 (depends on 20) The integrated circuit die of claim 20, wherein the multi-lane communication interface is a serial point-to-point link interface. ### Claim 22 (depends on 21) The integrated circuit die of claim 21, further comprising logical PHY circuitry coupled to the first link layer circuitry and the second link layer circuitry to prepare outgoing information for transmission by the electrical sub-block, the outgoing information comprising an error detection code associated with a flit. ### Claim 23 (depends on 22) The integrated circuit die of claim 22, wherein the flit is a multi-slotted flit. ### Claim 24 (depends on 23) The integrated circuit die of claim 23, wherein the error detection code is a CRC value. ### Claim 25 (depends on 24) The integrated circuit die of claim 24, wherein the error detection code is a 16-bit CRC value. ### Claim 26 (depends on 25) The integrated circuit die of claim 25, wherein the processor comprises a first processor core and a second processor core, wherein the first processor core and the second processor core are operable as independent nodes under control of a virtual machine monitor. ### Claim 27 (depends on 25) The integrated circuit die of claim 25, wherein the first protocol stack is an input/output (I/O) protocol stack. ### Claim 28 (depends on 25) The integrated circuit die of claim 25, wherein the first protocol stack is a network protocol stack. ### Claim 29 (depends on 16) The integrated circuit die of claim 16, wherein the memory access protocol stack is a coherent memory access protocol stack. ### Claim 30 (depends on 29) The integrated circuit die of claim 29, further comprising a first set of transmission paths to transmit serial data in accordance with the first layered protocol stack and a second set of transmission paths to transmit serial data in accordance with the second layered protocol stack. ### Claim 31 (depends on 30) The integrated circuit die of claim 30, wherein the first set of transmission paths and the second set of transmission paths comprise respective copper lines.