# US 2021/0240622 A1 · Selective endpoint isolation for self-healing in a cache and memory coherent system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240622 A1 - Document ID: US20210240622A1 - Status: Published application - Kind: A1 - Application number: 16/777,502 - Filed: 2020-01-30 - Published: 2021-08-05 - Earliest claimed: 2020-01-30 - Assignees: Microsoft Technology Licensing, LLC - Applicants: Microsoft Technology Licensing, LLC - Inventors: Perry Victor Lea - Web page: https://patentgrep.com/patent/US20210240622A1 ## CPC - G06F 12/0815: Cache consistency protocols - G06F 12/084: with a shared cache - G06F 9/45558: {Hypervisor-specific management and integration aspects} - G06F 11/0724: {in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80)} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/1417: {Boot up procedures} - G06F 11/1423: {by reconfiguration of paths} - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 11/3055: {Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available (error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction of the data by redundancy in operations G06F11/14; error detection or correction by redundancy in hardware G06F11/16)} - G06F 11/3476: {Data logging (G06F11/14, G06F11/2205 take precedence)} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 13/1668: {Details of memory controller} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package} - G06F 2009/45583: {Memory management, e.g. access or allocation} - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F 2213/0026: PCI express - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip. ## Claims ### Claim 1 A cache and memory coherent system comprising: multiple processing chips each hosting a different subset of a shared memory space; one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips; and a coherent mesh fabric that physically couples together each of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to detection of a defective hardware component and identification of a first processing chip of the multiple processing chips hosting the defective hardware component, the update to the one or more routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip. ### Claim 2 (depends on 1) The cache and memory coherent system of claim 1, wherein the coherent mesh fabric executes the routing logic to remove the access routes having the endpoints corresponding to the first processing chip without adding new access routes to the logical addresses identified by the removed access routes. ### Claim 3 (depends on 1) The cache and memory coherent system of claim 1, wherein the coherent mesh fabric includes a communication bus that uses a peripheral component interconnect express (PCIe) physical interface. ### Claim 4 (depends on 1) The cache and memory coherent system of claim 1, wherein the processing chips are system-on-chips (SoCs) arranged on a same printed circuit board assembly (PCBA). ### Claim 5 (depends on 1) The cache and memory coherent system of claim 1, further comprising a controller stored in memory and configured analyze system log information to identify the first processing chip hosting the defective hardware component of the multiple processing chips. ### Claim 6 (depends on 1) The cache and memory coherent system of claim 1, wherein the cache and memory coherent system is further configured to pool together resources on two or more of the processing chips to provide a user with a virtual machine experience. ### Claim 7 (depends on 1) The cache and memory coherent system of claim 1, wherein the coherent mesh fabric executes the routing logic for updating the one or more routing tables responsive to a reboot of the cache and memory coherent system. ### Claim 8 A method comprising: analyzing system log information to identify a location of a defective hardware component within a cache and memory coherent system, the cache and memory coherent system including multiple processing chips each hosting a different subset of a shared memory space; and responsive to determining that the location of the defective hardware component corresponds to a first processing chip of the multiple processing chips, updating one or more of routing tables to remove all access routes mapping logical addresses of the shared memory space to endpoints corresponding to the first processing chip. ### Claim 9 (depends on 8) The method of claim 8, wherein updating the one or more routing tables includes removing the access routes having the endpoints corresponding to the first processing chip without adding new access routes to the logical addresses identified by the removed access routes. ### Claim 10 (depends on 8) The method of claim 8, wherein the multiple processing chips are coupled together via a coherent mesh fabric including a communication bus that uses a peripheral component interconnect express (PCIe) physical interface. ### Claim 11 (depends on 8) The method of claim 8, wherein the processing chips are system-on-chips (SoCs) arranged on a same printed circuit board assembly (PCBA). ### Claim 12 (depends on 8) The method of claim 8, further comprising: generating a logfile including the system log information, the system log information being indicative of potentially defective hardware components hosted by any of the multiple processing chips. ### Claim 13 (depends on 8) The method of claim 8, wherein updating the one or more routing tables comprises updating a routing table stored on each of a plurality of different processing chips of the multiple processing chips. ### Claim 14 (depends on 10) The method of claim 10, wherein the coherent mesh fabric executes logic for updating the one or more routing tables responsive to a reboot of the cache and memory coherent system. ### Claim 15 One or more tangible computer-readable storage media encoding computer-executable instructions for executing a computer process comprising: analyzing system log information to identify a location of a defective hardware component within cache and memory coherent system, the cache and memory coherent system including multiple processing chips each hosting a different subset of a shared memory space; and responsive to determining that the location of the defective hardware component corresponds to a first processing chip of the multiple processing chips, updating one or more of routing tables to remove all access routes mapping logical addresses of the shared memory space to endpoints corresponding to the first processing chip. ### Claim 16 (depends on 15) The one or more tangible computer-readable storage media of claim 15, wherein the multiple processing chips are coupled together via a coherent mesh fabric including a communication bus that uses a peripheral component interconnect express (PCIe) physical interface. ### Claim 17 (depends on 15) The one or more tangible computer-readable storage media of claim 15, wherein the processing chips are system-on-chips (SoCs) arranged on a same printed circuit board assembly (PCBA). ### Claim 18 (depends on 15) The one or more tangible computer-readable storage media of claim 15, wherein updating the one or more routing tables includes removing the access routes having the endpoints corresponding to the first processing chip without adding new access routes to the logical addresses identified by the removed access routes. ### Claim 19 (depends on 15) The one or more tangible computer-readable storage media of claim 15, wherein updating the one or more routing tables comprises updating a routing table stored on each of a plurality of different processing chips of the multiple processing chips. ### Claim 20 (depends on 15) The one or more tangible computer-readable storage media of claim 15, updating the one or more routing tables is performed responsive to a reboot of the cache and memory coherent system.