# US 2021/0240620 A1 · Memory module with local synchronization and method of operation

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- Number: US 2021/0240620 A1
- Document ID: US20210240620A1
- Status: Published application
- Kind: A1
- Application number: 17/141,978
- Filed: 2021-01-05
- Published: 2021-08-05
- Earliest claimed: 2013-07-27
- Assignees: Netlist, Inc.
- Applicants: Netlist, Inc.
- Inventors: Hyun Lee; Jayesh R. Bhakta
- Web page: https://patentgrep.com/patent/US20210240620A1

## CPC

- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G06F 13/4243: {with synchronous protocol}
- G06F 13/4256: {using a clocked protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.

## Claims

### Claim 1

A memory module operable in a computer system having a memory controller and a system bus including one or more clock signal lines, a set of control signal lines and a plurality of sets of n-bit wide data/strobe signal lines, where n is an integer larger than one, comprising:
a control circuit configurable to receive a system clock from the memory controller via the one or more clock signal lines, and input address and control (C/A) signals from the memory controller via the set of control signal lines, and to output a module clock signal, module C/A signals and data buffer control signals in response to the system clock and the input C/A signals;
memory devices organized in one or more ranks; and
a plurality of data buffers configurable to receive the module clock signal and the data buffer control signals from the control circuit; wherein:
a respective data buffer of the plurality of data buffers is coupled to a respective group of the memory devices and includes a respective n-bit-wide data path and logic configurable to control the respective n-bit-wide data path in response to the data buffer control signals, the respective group of the memory devices including at least one memory device in each of the one or more ranks, the respective n-bit-wide data path including at least one programmable delay element controlled by the logic;
the respective data buffer is configurable to generate, in response to receiving the module clock signal, a respective local clock signal that is phase-locked with the module clock signal and has a respective programmable delay from the module clock signal; and
the respective group of the memory devices is configurable to receive the module C/A signals from the control circuit and the respective local clock signal, and to communicate respective data and data strobe signals with the memory controller in response to the module C/A signals and the respective local clock signal, the respective data and data strobe signals being communicated via the respective n-bit wide data path and a respective set of the plurality of sets of n-bit wide data/strobe signal lines.