# US 2021/0240619 A1 · Speculation-restricted memory region type > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240619 A1 - Document ID: US20210240619A1 - Status: Published application - Kind: A1 - Application number: 17/052,701 - Filed: 2019-05-09 - Published: 2021-08-05 - Earliest claimed: 2018-06-01 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Richard William EARNSHAW - Web page: https://patentgrep.com/patent/US20210240619A1 ## CPC - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 9/3842: {Speculative instruction execution} - G06F 12/145: {the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism} - G06F 2212/1052: Security improvement - G06F 2212/507: using speculative control - G06F 2212/60: Details of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus has processing circuitry (18), and memory access circuitry (35) to control access to a memory system based on memory attribute data identifying each memory region as one of a plurality of region types. A speculation-restricted region type is supported, for which: at least when a first read request is non-speculatively issued to a region of the speculation-restricted type, a subsequent read request is permitted to be serviced using data obtained in response to the first read request; and for a speculatively issued read request to the region of the speculation-restricted type, at least when caching the read data would require allocation of a new entry in the cache, at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, may be prohibited from being performed before the first read request has been resolved as correct. ## Claims ### Claim 1 An apparatus comprising: processing circuitry capable of speculatively issuing a read request to request that data is read from a target memory region of a memory system; and memory access circuitry to control access to the memory system based on memory attribute data identifying each memory region as one of a plurality of region types; in which: in response to a first read request for which the target memory region is indicated as a speculation-restricted region type by the memory attribute data: at least when the first read request is non-speculatively issued by the processing circuitry, the memory access circuitry is configured to permit a subsequent read request to be serviced using data obtained in response to the first read request; and when the first read request is speculatively issued by the processing circuitry, at least when storage of data obtained in response to the first read request in a cache of the processing circuitry would require allocation of a new entry in the cache, the memory access circuitry is configured to prohibit at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, from being performed before the processing circuitry has resolved whether the first read request is correct. ### Claim 2 (depends on 1) The apparatus according to claim 1, in which said at least one response action comprises an action having potential to cause an effect which is detectable through measuring cache access timings or memory system access timings. ### Claim 3 (depends on 1) The apparatus according to claim 1, in which said at least one response action comprises issuing a read transaction to the memory system in response to the first read request from the processing circuitry. ### Claim 4 (depends on 1) The apparatus according to claim 1, in which said at least one response action comprises returning data obtained from the memory system in response to the read request to the processing circuitry. ### Claim 5 (depends on 1) The apparatus according to claim 1, in which said at least one response action comprises allocating a new entry in said cache for storing data corresponding to the target memory region. ### Claim 6 (depends on 1) The apparatus according to claim 1, in which when the first read request is speculatively issued by the processing circuitry and prior to issue of the first read request an entry has already been allocated in said cache for storing data corresponding to the target memory region, the memory access circuitry is configured to prohibit said at least one response action from being performed before the processing circuitry has resolved whether the first read request is correct. ### Claim 7 (depends on 1) The apparatus according to claim 1, in which when the first read request is speculatively issued by the processing circuitry and prior to issue of the first read request an entry has already been allocated in said cache for storing data corresponding to the target memory region, the memory access circuitry is configured to allow said at least one response action to be performed before the processing circuitry has resolved whether the first read request is correct. ### Claim 8 (depends on 1) The apparatus according to claim 1, in which said at least one response action comprises triggering a change in which addresses have data allocated in at least one remote cache of a master device other than the processing circuitry. ### Claim 9 (depends on 1) The apparatus according to claim 1, in which said at least one response action comprises causing an unopened DRAM page of the memory system to be opened. ### Claim 10 (depends on 1) The apparatus according to claim 1, in which said cache comprises a level 1 cache of the processing circuitry. ### Claim 11 (depends on 1) The apparatus according to claim 1, in which: when the first read request is speculatively issued by the processing circuitry, at least when storage of data obtained in response to the first read request in the cache would require allocation of a new entry in the cache, the memory access circuitry is configured to prohibit said at least one response action being performed in response to the first read request even when the processing circuitry has already resolved that the first read request is correct. ### Claim 12 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to reject speculatively issued read requests for which the target memory region is of the speculation-restricted region type. ### Claim 13 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to permit unaligned memory accesses to a memory region of the speculation-restricted region type. ### Claim 14 (depends on 1) The apparatus according to claim 1, in which the cache of the processing circuitry is configured to limit a maximum duration for which data corresponding to a memory region of the speculation-restricted region type can remain cached in the cache. ### Claim 15 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to prohibit a prefetch request to prefetch data from a memory region of the speculation-restricted region type into the cache. ### Claim 16 (depends on 1) The apparatus according to claim 1, in which the memory access circuitry is configured to prohibit a prefetch request to prefetch data from a given memory region of the speculation-restricted region type into the cache unless data corresponding to a previous memory region immediately preceding the given memory region in a memory address space is already non-speculatively cached in the cache. ### Claim 17 (depends on 15) The apparatus according to claim 15, in which said prefetch request comprises one of: a hardware prefetch request generated by a hardware prefetcher independent of instructions executed by the processing circuitry; and a software prefetch request triggered by a software prefetch instruction executed by the processing circuitry. ### Claim 18 (depends on 1) The apparatus according to claim 1, in which in response to a given read request for which the target memory region is indicated as a device region type by the memory attribute data, the memory access circuitry is configured to prohibit a subsequent read request from being serviced using data obtained in response to the given read request. ### Claim 19 (depends on 1) The apparatus according to claim 1, in which in response to a read request for which the target memory region is indicated as a non-speculation-restricted region type by the memory attribute data, the memory access circuitry is configured to determine whether said at least one response action is permitted independent of whether the read request is issued speculatively or non-speculatively. ### Claim 20 (depends on 19) The apparatus according to claim 19, in which the memory access attribute data comprises a type attribute specified for each memory region, and the memory access circuitry is configured to determine that a given memory region is of: the non-speculation-restricted region type when the type attribute for the given memory region has a first value; and the speculation-restricted region type when the type attribute for the given memory region has a second value. ### Claim 21 (depends on 19) The apparatus according to claim 19, in which the memory access attribute data comprises a type attribute specified for each memory region, and a global attribute shared between a plurality of memory regions; and when the type attribute for a given memory region has a predetermined value, the memory access circuitry is configured to determine that the given memory region is of: the non-speculation-restricted region type when the global attribute has a first value; and the speculation-restricted region type when the global attribute has a second value. ### Claim 22 A method for a data processing apparatus comprising processing circuitry capable of speculatively issuing a read request to request that data is read from a target memory region of a memory system; the method comprising: controlling access to the memory system based on memory attribute data identifying each memory region as one of a plurality of region types; and in response to a first read request for which the target memory region is indicated as a speculation-restricted region type by the memory attribute data: at least when the first read request is non-speculatively issued by the processing circuitry, permitting a subsequent read request to be serviced using data obtained in response to the first read request; and when the first read request is speculatively issued by the processing circuitry, at least when storage of data obtained in response to the first read request in a cache of the processing circuitry would require allocation of a new entry in the cache, prohibiting at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, from being performed before the processing circuitry has resolved whether the first read request is correct. ### Claim 23 A method for memory allocation for a data processing apparatus, comprising: allocating one or more regions of memory for use by a given software process; and for each allocated region, selecting a selected region type from among a plurality of region types, and storing memory attribute data identifying the selected region type; in which: for at least one region, the selected region type comprises a speculation-restricted region type indicating that, in response to a first read request requesting that data is read from said at least one region, the data processing apparatus is to: at least when the first read request is non-speculatively issued by the data processing apparatus, permit a subsequent read request to be serviced using data obtained in response to the first read request; and when the first read request is speculatively issued by the data processing apparatus, at least when storage of data obtained in response to the first read request in a cache of the data processing apparatus would require allocation of a new entry in the cache, prohibit at least one response action from being performed before the data processing apparatus has resolved whether the first read request is correct, where said at least one response action is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type. ### Claim 24 (depends on 23) A non-transitory storage medium storing a computer program for controlling a host processing apparatus to perform the method of claim 23. ### Claim 25 (canceled)