# US 2021/0240567 A1 · System and method to run basic input/output system code from a non-volatile memory express device boot partition > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240567 A1 - Document ID: US20210240567A1 - Status: Published application - Kind: A1 - Application number: 16/780,464 - Filed: 2020-02-03 - Published: 2021-08-05 - Earliest claimed: 2020-02-03 - Assignees: Dell Products L.P. - Applicants: Dell Products, LP - Inventors: Isaac S. Hsu; Lip Vui Simon Kan; Adolfo S. Montero - Web page: https://patentgrep.com/patent/US20210240567A1 ## CPC - G06F 11/1417: {Boot up procedures} - G06F 9/4406: {Loading of operating system} - G06F 9/4408: {Boot device selection} - G06F 11/0772: {Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers} - G06F 11/1469: {Backup restoration techniques} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An information handling system may include an embedded controller, a serial peripheral interface (SPI) read-only memory (ROM) device to store a first basic input/output system (BIOS) firmware for the information handling system, and a non-volatile memory device includes a boot partition to store a second BIOS firmware. The embedded controller detects a failure during a boot process, switches a first SPI of a chipset from the SPI ROM to the embedded controller and executes the second BIOS firmware from the non-volatile memory device via a sideband access of the non-volatile memory device. ## Claims ### Claim 1 An information handling system, comprising: an embedded controller; a serial peripheral interface (SPI) read-only memory (ROM) device to store a first basic input/output system (BIOS) firmware for the information handling system; and a non-volatile memory device including a boot partition to store a second BIOS firmware, wherein the embedded controller detects a failure during a boot process, switches a first SPI of a chipset from the SPI ROM to the embedded controller and executes the second BIOS firmware from the non-volatile memory device via a sideband access of the non-volatile memory device. ### Claim 2 (depends on 1) The information handling system of claim 1, wherein the second BIOS firmware is a copy of the first BIOS firmware. ### Claim 3 (depends on 1) The information handling system of claim 1, wherein the embedded controller executes the second BIOS firmware from the boot partition of the non-volatile memory device. ### Claim 4 (depends on 1) The information handling system of claim 1, wherein the non-volatile memory device is a non-volatile memory-express (NVMe) solid state drive. ### Claim 5 (depends on 1) The information handling system of claim 1, wherein the second BIOS firmware is a copy of the first BIOS firmware. ### Claim 6 (depends on 1) The information handling system of claim 1, wherein the second BIOS firmware is used to recover the first BIOS firmware. ### Claim 7 (depends on 1) The information handling system of claim 1, wherein the failure is an invalid first BIOS firmware. ### Claim 8 (depends on 1) The information handling system of claim 1, wherein the failure is an SPI ROM hardware failure. ### Claim 9 (depends on 1) The information handling system of claim 1, wherein the sideband access of the non-volatile memory device is via a second SPI. ### Claim 10 (depends on 1) The information handling system of claim 1, wherein the embedded controller is connected to the chipset via an enhanced SPI and the non-volatile memory device via a second SPI. ### Claim 11 (depends on 1) The information handling system of claim 1, wherein the embedded controller is connected to the chipset via an enhanced SPI and the non-volatile memory device via a system management bus. ### Claim 12 (depends on 1) The information handling system of claim 1, wherein the boot partition of the non-volatile memory device emulates a virtual SPI ROM device. ### Claim 13 (depends on 1) The information handling system of claim 1, wherein the second BIOS firmware is encrypted. ### Claim 14 An information handling system, comprising: an embedded controller; a serial peripheral interface (SPI) read-only memory (ROM) device to store a first basic input/output system (BIOS) code for the information handling system; and a non-volatile memory device including a boot partition to store a second BIOS firmware, wherein the embedded controller detects a failure during a boot process, switches an SPI of a chipset from the SPI ROM to the embedded controller and recovers the first BIOS firmware based on the second BIOS firmware from the non-volatile memory device via an out-of-band network access. ### Claim 15 (depends on 14) The information handling system of claim 14, wherein the out-of-band network access of the non-volatile memory device is a second SPI. ### Claim 16 (depends on 14) The information handling system of claim 14, wherein the embedded controller is connected to the chipset via an enhanced SPI and the non-volatile memory device via a second SPI. ### Claim 17 (depends on 14) The information handling system of claim 14, wherein the boot partition of the non-volatile memory device emulates a virtual SPI ROM device. ### Claim 18 A method comprising: storing a first basic input/output system (BIOS) firmware in a serial peripheral interface (SPI) read-only memory (ROM) device of an information handling system; storing a second BIOS firmware in a boot partition of a non-volatile memory-express device, wherein the boot partition of the non-volatile memory-express device can be accessed via an out-of-band network access; detecting a hardware failure during a boot process of the information handling system; switching an SPI of a chipset of the information handling system from the SPI ROM to an embedded controller; and recovering the first BIOS firmware in the SPI ROM based on the second BIOS firmware via the out-of-band network access. ### Claim 19 (depends on 18) The method of claim 18, wherein the embedded controller is connected to the chipset via an enhanced SPI and the non-volatile memory-express device via a second SPI. ### Claim 20 (depends on 18) The method of claim 18, wherein the boot partition of the non-volatile memory-express device emulates a virtual SPI ROM device.