# US 2021/0240480 A1 · A system and method for handling exception causing events > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240480 A1 - Document ID: US20210240480A1 - Status: Published application - Kind: A1 - Application number: 17/269,938 - Filed: 2019-10-16 - Published: 2021-08-05 - Earliest claimed: 2018-12-06 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Alasdair GRANT - Web page: https://patentgrep.com/patent/US20210240480A1 ## CPC - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/4812: {by interrupt, e.g. masked} - G06F 9/3881: {Arrangements for communication of instructions and data} - G06F 9/542: {Event management; Broadcasting; Multicasting; Notifications} - G06F 11/3656: {using a specific debug interface} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method are provided for handling exception causing events. A first processing unit is provided for executing program code, and a second processing unit is also provided. The first processing unit has a control interface mapped to the memory address space of the second processing unit and configured to provide the second processing unit with direct mapped access to state information of the first processing unit. The first processing unit is responsive to at least one exception causing event to enter a halted mode where the first processing unit stops execution of the program code and issues a trigger event. The second processing unit is responsive to the trigger event to execute an exception handling routine during which the second processing unit is arranged to access the state information of the first processing unit via the control interface in order to modify the state information as required by the exception handling routine. The second processing unit is arranged on completion of the exception handling routine to cause the first processing unit to exit the halted mode and resume execution of the program code. Such an approach allows for physical separation between the program code being executed by the first processing unit and the software used to perform the exception handling routine, which can give rise to significant security improvements within the system. ## Claims ### Claim 1 A system comprising: a first processing unit to execute program code; and a second processing unit; the first processing unit having a control interface mapped to memory address space of the second processing unit and configured to provide the second processing unit with direct mapped access to state information of the first processing unit; the first processing unit being responsive to at least one exception causing event to enter a halted mode where the first processing unit stops execution of the program code and issues a trigger event; the second processing unit being responsive to the trigger event to execute an exception handling routine during which the second processing unit is arranged to access the state information of the first processing unit via the control interface in order to modify the state information as required by the exception handling routine; the second processing unit being arranged on completion of the exception handling routine to cause the first processing unit to exit the halted mode and resume execution of the program code. ### Claim 2 (depends on 1) A system as claimed in claim 1, wherein the state information of the first processing unit comprises content of a set of registers of the first processing unit used to store data processed by the first processing unit when executing the program code. ### Claim 3 (depends on 2) A system as claimed in claim 2, wherein the control interface provides a set of storage elements mapped to the memory address space of the second processing unit to provide direct mapped access to the set of registers by the second processing unit. ### Claim 4 (depends on 1) A system as claimed in claim 1, wherein the state information of the first processing unit comprises data stored in at least a portion of memory address space of the first processing unit. ### Claim 5 (depends on 4) A system as claimed in claim 4, wherein said at least a portion of the memory address space of the first processing unit forms a secondary address space of the second processing unit. ### Claim 6 (depends on 4) A system as claimed in claim 4, wherein the control interface provides a block of storage elements mapped to the memory address space of the second processing unit, each storage element in the block being directly mapped to a corresponding memory location within said at least a portion of the memory address space of the first processing unit. ### Claim 7 (depends on 6) A system as claimed in claim 6, wherein the control interface comprises configurable mapping storage to identify the direct mapping between the storage elements in the block of storage elements and the corresponding memory locations within said at least a portion of the memory address space of the first processing unit. ### Claim 8 (depends on 1) A system as claimed in claim 1, wherein the control interface comprises configurable exception event identifying storage to identify which exception causing events, when encountered during execution of the program code by the first processing unit, are to cause the first processing unit to enter the halted mode and issue the trigger event. ### Claim 9 (depends on 1) A system as claimed in claim 1, wherein the exception event identifying storage is configured to identify that the first processing unit is to enter the halted mode and issue the trigger event whenever an exception causing event occurs which would require the first processing unit transitioning to a specified exception level were the exception causing event to be handled by the first processing unit. ### Claim 10 (depends on 1) A system as claimed in claim 1, wherein the first processing unit is arranged to remain at its current exception level when entering the halted mode, and the second processing unit is arranged to execute the exception handling routine at a chosen exception level. ### Claim 11 (depends on 10) A system as claimed in claim 10, wherein the chosen exception level is an exception level higher than the current exception level of the first processing unit. ### Claim 12 (depends on 1) A system as claimed in claim 1, wherein the control interface comprises syndrome storage mapped to the memory address space of the second processing unit and written to by the first processing unit to provide information used by the second processing unit to assist in identifying why the first processing unit entered the halted mode. ### Claim 13 (depends on 1) A system as claimed in claim 1, further comprising: a third processing unit having a further control interface mapped to memory address space of the second processing unit and configured to provide the second processing unit with direct mapped access to state information of the third processing unit; the third processing unit being responsive to at least one exception causing event to enter the halted mode where the third processing unit stops execution and issues the trigger event; the trigger event comprising information enabling the second processing unit to determine whether the trigger event was issued by the first processing unit or the third processing unit, and thus determine which of the first and third processing units to access when executing the exception handling routine. ### Claim 14 (depends on 1) A system as claimed in claim 1, further comprising: an additional processing unit; the second processing unit having a second control interface mapped to memory address space of the additional processing unit and configured to provide the additional processing unit with direct mapped access to state information of the second processing unit; the second processing unit being responsive to at least one exception causing event to enter the halted mode where the second processing unit stops execution of program code being run on the second processing unit, and issues a further trigger event; the additional processing unit being responsive to the further trigger event to execute a further exception handling routine during which the additional processing unit is arranged to access the state information of the second processing unit via the second control interface in order to modify that state information as required by the further exception handling routine; the additional processing unit being arranged on completion of the further exception handling routine to cause the second processing unit to exit the halted mode and resume execution of the program code being run on the second processing unit. ### Claim 15 (depends on 1) A system as claimed in claim 1, wherein the first processing unit is an application processing unit and the program code is application program code, and the second processing unit is a control processing unit. ### Claim 16 (depends on 1) A system as claimed in claim 1, wherein the first processing unit and the second processing unit are provided by separate processor cores. ### Claim 17 (depends on 1) A system as claimed in claim 1, wherein the first processing unit and the second processing unit have separate cache structures for at least a subset of the cache levels within the system. ### Claim 18 (depends on 1) A system as claimed in claim 1, wherein the first processing unit and the second processing unit are provided by separate threads on a multi-threaded processor core. ### Claim 19 (depends on 1) An apparatus as claimed in claim 1, wherein at least one of the first processing unit and the second processing unit is constrained to only operate at a single exception level. ### Claim 20 (depends on 1) An apparatus as claimed in claim 1, wherein the second processing unit is one of: a targeted processing unit to which the trigger event is issued; a processing unit amongst several processing units that is capable of responding to the trigger event. ### Claim 21 A first processing unit comprising: execution circuitry to execute program code; and a control interface mapped to memory address space of a second processing unit and configured to provide the second processing unit with direct mapped access to state information of the first processing unit; the first processing unit being responsive to at least one exception causing event to enter a halted mode where the execution circuitry stops execution of the program code, and a trigger event is issued; the control interface being arranged to be accessible to the second processing unit whilst the second processing unit is executing an exception handling routine in response to the trigger event, to enable the second processing unit to access and modify the state information of the first processing unit as required by the exception handling routine; the first processing unit being arranged, when the second processing unit has completed the exception handling routine, to exit the halted mode and resume execution of the program code. ### Claim 22 A second processing unit comprising: execution circuitry to execute an exception handling routine in response to a trigger event issued by a first processing unit, the trigger event indicating that the first processing unit has entered a halted mode where execution of program code by the first processing unit has been halted; and a communication interface via which the second processing circuitry is arranged to access a control interface of the first processing unit whilst executing the exception handling routine, the control interface being mapped to memory address space of the second processing unit and configured to provide the second processing unit with direct mapped access to state information of the first processing unit; the second processing unit being arranged to access the state information of the first processing unit via the control interface in order to modify the state information as required by the exception handling routine; and the second processing unit being arranged on completion of the exception handling routine to cause the first processing unit to exit the halted mode and resume execution of the program code. ### Claim 23 A method of handling exception causing events in a system having a first processing unit to execute program code, and a second processing unit, comprising: providing the first processing unit with a control interface mapped to memory address space of the second processing unit and configured to provide the second processing unit with direct mapped access to state information of the first processing unit; responsive to at least one exception causing event within the first processing unit, causing the first processing unit to enter a halted mode where the first processing unit stops execution of the program code, and issues a trigger event; causing the second processing unit to be responsive to the trigger event to execute an exception handling routine during which the second processing unit accesses the state information of the first processing unit via the control interface in order to modify the state information as required by the exception handling routine; and on completion of the exception handling routine by the second processing unit, causing the first processing unit to exit the halted mode and resume execution of the program code.