# US 2021/0240475 A1 · Apparatuses, methods, and systems for instructions to request a history reset of a processor core > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240475 A1 - Document ID: US20210240475A1 - Status: Published application - Kind: A1 - Application number: 17/124,813 - Filed: 2020-12-17 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: ELIEZER WEISSMANN; MARK CHARNEY; MICHAEL MISHAELI; ROBERT VALENTINE; ITAI RAVID; JASON W. BRANDT; GILBERT NEIGER; BARUCH CHAIKIN; EFRAIM ROTEM - Web page: https://patentgrep.com/patent/US20210240475A1 ## CPC - G06F 9/30101: {Special purpose registers} - G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables} - G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler. ## Claims ### Claim 1 A hardware processor comprising: a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a control register; and an execution circuit to execute the decoded single instruction to: check that an enable bit of the control register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler. ### Claim 2 (depends on 1) The hardware processor of claim 1, wherein, when the enable bit is set, the execution circuit is to execute the decoded single instruction to reset the plurality of software thread runtime property histories of the hardware guide scheduler without modifying other architectural state of the hardware processor. ### Claim 3 (depends on 1) The hardware processor of claim 1, wherein an opcode of the single instruction is a legacy opcode, and when the enable bit is not set, the execution circuit is to execute the single instruction as a no-operation. ### Claim 4 (depends on 1) The hardware processor of claim 1, wherein, when the enable bit is set, the execution circuit is to execute the decoded single instruction to reset the plurality of software thread runtime property histories of the hardware guide scheduler only when the single instruction is requested for execution by an operating system. ### Claim 5 (depends on 1) The hardware processor of claim 1, wherein the plurality of software thread runtime property histories comprises a plurality of weights for respective classes of performance monitoring events for a plurality of cores of the hardware processor. ### Claim 6 (depends on 5) The hardware processor of claim 5, wherein the respective classes comprise a first class for a first type of core and a second class for a second, higher performance core. ### Claim 7 (depends on 5) The hardware processor of claim 5, wherein the respective classes comprise a first class for an integer type of vector instruction and a second class for a floating-point type of vector instruction. ### Claim 8 (depends on 1) The hardware processor of claim 1, wherein the hardware guide scheduler is to store a hint for a next software thread that is to be executed on the hardware processor, in a register of the hardware processor to indicate to an operating system a core type of a plurality of cores types of the hardware processor, and the hint is based on the plurality of software thread runtime property histories. ### Claim 9 A method comprising: generating a plurality of software thread runtime property histories with a hardware guide scheduler of a hardware processor; decoding a single instruction into a decoded single instruction with a decoder of the hardware processor, the single instruction having a field that identifies a control register; and executing the decoded single instruction with an execution circuit of the hardware processor to: check that an enable bit of the control register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler. ### Claim 10 (depends on 9) The method of claim 9, wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler without modifying other architectural state of the hardware processor. ### Claim 11 (depends on 9) The method of claim 9, wherein an opcode of the single instruction is a legacy opcode, and when the enable bit is not set, the execution circuit executes the single instruction as a no-operation. ### Claim 12 (depends on 9) The method of claim 9, wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler only when the single instruction is requested for execution by an operating system. ### Claim 13 (depends on 9) The method of claim 9, wherein the plurality of software thread runtime property histories comprises a plurality of weights for respective classes of performance monitoring events for a plurality of cores of the hardware processor. ### Claim 14 (depends on 13) The method of claim 13, wherein the respective classes comprise a first class for a first type of core and a second class for a second, higher performance core. ### Claim 15 (depends on 13) The method of claim 13, wherein the respective classes comprise a first class for an integer type of vector instruction and a second class for a floating-point type of vector instruction. ### Claim 16 (depends on 9) The method of claim 9, further comprising storing a hint, by the hardware guide scheduler, for a next software thread that is to be executed on the hardware processor, in a register of the hardware processor to indicate to an operating system a core type of a plurality of cores types of the hardware processor, and the hint is based on the plurality of software thread runtime property histories. ### Claim 17 A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising: decoding a single instruction into a decoded single instruction with a decoder of a hardware processor, the single instruction having a field that identifies a control register; and executing the decoded single instruction with an execution circuit of the hardware processor to: check that an enable bit of the control register is set, and when the enable bit is set, to reset a plurality of software thread runtime property histories of a hardware guide scheduler of the hardware processor. ### Claim 18 (depends on 17) The non-transitory machine readable medium of claim 17, wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler without modifying other architectural state of the hardware processor. ### Claim 19 (depends on 17) The non-transitory machine readable medium of claim 17, wherein an opcode of the single instruction is a legacy opcode, and when the enable bit is not set, the execution circuit executes the single instruction as a no-operation. ### Claim 20 (depends on 17) The non-transitory machine readable medium of claim 17, wherein, when the enable bit is set, the executing the decoded single instruction resets the plurality of software thread runtime property histories of the hardware guide scheduler only when the single instruction is requested for execution by an operating system. ### Claim 21 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the plurality of software thread runtime property histories comprises a plurality of weights for respective classes of performance monitoring events for a plurality of cores of the hardware processor. ### Claim 22 (depends on 21) The non-transitory machine readable medium of claim 21, wherein the respective classes comprise a first class for a first type of core and a second class for a second, higher performance core. ### Claim 23 (depends on 21) The non-transitory machine readable medium of claim 21, wherein the respective classes comprise a first class for an integer type of vector instruction and a second class for a floating-point type of vector instruction. ### Claim 24 (depends on 17) The non-transitory machine readable medium of claim 17, further comprising storing a hint, by the hardware guide scheduler, for a next software thread that is to be executed on the hardware processor, in a register of the hardware processor to indicate to an operating system a core type of a plurality of cores types of the hardware processor, and the hint is based on the plurality of software thread runtime property histories. ### Claim 25 (depends on 17) The non-transitory machine readable medium of claim 17, further comprising translating the single instruction into one or more instructions of a different instruction set architecture prior to the decoding, wherein executing of the one or more instructions of the different instruction set architecture is to be functionally equivalent as the executing of the decoded single instruction.