# US 2021/0240447 A1 · Fast digital multiply-accumulate (mac) by fast digital multiplication circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2021/0240447 A1 - Document ID: US20210240447A1 - Status: Published application - Kind: A1 - Application number: 16/778,749 - Filed: 2020-01-31 - Published: 2021-08-05 - Earliest claimed: 2020-01-31 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Xia LI; Zhongze WANG; Periannan CHIDAMBARAM - Web page: https://patentgrep.com/patent/US20210240447A1 ## CPC - G06F 7/5334: {by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 7/523: Multiplying only - G06F 7/5324: {partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers} - G06F 2207/4824: Neural networks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals. ## Claims ### Claim 1 A circuit for digital signal processing, comprising: a first multiplier circuit configured to multiply a first portion of a first digital input signal with a first portion of a second digital input signal to generate a first multiplication signal; a second multiplier circuit configured to multiply a second portion of the first digital input signal with a second portion of the second digital input signal to generate a second multiplication signal; a first adder circuit configured to add the first portion and the second portion of the first digital input signal to generate a first addition signal; a second adder circuit configured to add the first portion and the second portion of the second digital input signal to generate a second addition signal; a third multiplier circuit configured to multiply the first addition signal and the second addition signal to generate a third multiplication signal; a third adder circuit configured to add the first multiplication signal and the second multiplication signal to generate a third addition signal; a subtraction circuit configured to subtract the third addition signal from the third multiplication signal to generate a subtraction signal; and one or more adder circuits configured to add a left-shifted version of the first multiplication signal, the second multiplication signal, and a left-shifted version of the subtraction signal. ### Claim 2 (depends on 1) The circuit of claim 1, wherein: the first portion of the first digital input signal comprises one or more most significant bits (MSBs) of the first digital input signal; the first portion of the second digital input signal comprises one or more MSBs of the second digital input signal; the second portion of the first digital input signal comprises one or more least significant bits (LSBs) of the first digital input signal; and the second portion of the second digital input signal comprises one or more LSBs of the second digital input signal. ### Claim 3 (depends on 2) The circuit of claim 2, wherein a quantity of bits of each of the first digital input signal and the second digital input signal is n, wherein the one or more MSBs of the first digital input signal comprises n/2 bits, wherein the one or more MSBs of the second digital input signal comprises n/2 bits, wherein the one or more LSBs of the first digital input signal comprises n/2 bits, and wherein the one or more LSBs of the second digital input signal comprises n/2 bits. ### Claim 4 (depends on 1) The circuit of claim 1, further comprising an interface configured to left-shift bits of the first multiplication signal to generate the left-shifted version of the first multiplication signal. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the interface comprises a left-shift circuit. ### Claim 6 (depends on 4) The circuit of claim 4, wherein the interface is configured to left-shift the bits of the first multiplication signal by n bits, n representing a quantity of bits of the first digital input signal. ### Claim 7 (depends on 1) The circuit of claim 1, further comprising an interface configured to left-shift bits of the subtraction signal to generate the left-shifted version of the subtraction circuit. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the interface comprises a left-shift circuit. ### Claim 9 (depends on 7) The circuit of claim 7, wherein the interface is configured to left-shift the bits of the subtraction signal by n/2 bits, n representing a quantity of bits of the first digital input signal. ### Claim 10 (depends on 1) The circuit of claim 1, wherein the one or more adder circuits comprise: a fourth adder circuit configured to add the second multiplication signal and the left-shifted version of the first multiplication signal to generate a fourth addition signal; and a fifth adder circuit configured to add the fourth addition signal and the left-shifted version of the subtraction signal. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the fourth adder circuit is a half adder (HA), and wherein the fifth adder circuit is a full adder (FA). ### Claim 12 (depends on 1) The circuit of claim 1, wherein the first adder circuit, the second adder circuit, the third adder circuit, and the subtraction circuit are full adders (FAs). ### Claim 13 (depends on 1) The circuit of claim 1, wherein the subtraction circuit comprises an adder having an inverting input and a non-inverting input, wherein the third addition signal is provided to the inverting input, and wherein the third multiplier circuit is provided to the non-inverting input. ### Claim 14 A method for digital signal processing, comprising: multiplying, via a first multiplier circuit, a first portion of a first digital input signal with a first portion of a second digital input signal to generate a first multiplication signal; multiplying, via a second multiplier circuit, a second portion of the first digital input signal with a second portion of the second digital input signal to generate a second multiplication signal; adding, via a first adder circuit, the first portion and the second portion of the first digital input signal to generate a first addition signal; adding, via a second adder circuit, the first portion and the second portion of the second digital input signal to generate a second addition signal; multiplying, via a third multiplier circuit, the first addition signal and the second addition signal to generate a third multiplication signal; adding, via a third adder circuit, the first multiplication signal and the second multiplication signal to generate a third addition signal; subtracting, via a subtraction circuit, the third addition signal from the third multiplication signal to generate a subtraction signal; and adding, via one or more adder circuits, a left-shifted version of the first multiplication signal, the second multiplication signal, and a left-shifted version of the subtraction signal. ### Claim 15 (depends on 14) The method of claim 14, wherein: the first portion of the first digital input signal comprises one or more most significant bits (MSBs) of the first digital input signal; the first portion of the second digital input signal comprises one or more MSBs of the second digital input signal; the second portion of the first digital input signal comprises one or more least significant bits (LSBs) of the first digital input signal; and the second portion of the second digital input signal comprises one or more LSBs of the second digital input signal. ### Claim 16 (depends on 15) The method of claim 15, wherein a quantity of bits of each of the first digital input signal and the second digital input signal is n, wherein the one or more MSBs of the first digital input signal comprises n/2 bits, wherein the one or more MSBs of the second digital input signal comprises n/2 bits, wherein the one or more LSBs of the first digital input signal comprises n/2 bits, and wherein the one or more LSBs of the second digital input signal comprises n/2 bits. ### Claim 17 (depends on 14) The method of claim 14, further comprising left-shifting bits of the first multiplication signal to generate the left-shifted version of the first multiplication signal, wherein the bits of the first multiplication signal are left-shifted by n bits, n representing a quantity of bits of the first digital input signal. ### Claim 18 (depends on 14) The method of claim 14, further comprising left-shifting bits of the subtraction signal to generate the left-shifted version of the subtraction circuit, wherein the bits of the subtraction signal are left-shifted by n/2 bits, n representing a quantity of bits of the first digital input signal. ### Claim 19 (depends on 14) The method of claim 14, wherein adding the left-shifted version of the first multiplication signal, the second multiplication signal, and the left-shifted version of the subtraction signal comprises: adding, via a fourth adder circuit, the left-shifted version of the first multiplication signal and the second multiplication signal to generate a fourth addition signal; and adding, via a fifth adder circuit, the fourth addition signal and the left-shifted version of the subtraction signal. ### Claim 20 An apparatus for digital signal processing, comprising: means for multiplying a first portion of a first digital input signal with a first portion of a second digital input signal to generate a first multiplication signal; means for multiplying a second portion of the first digital input signal with a second portion of the second digital input signal to generate a second multiplication signal; means for adding the first portion and the second portion of the first digital input signal to generate a first addition signal; means for adding the first portion and the second portion of the second digital input signal to generate a second addition signal; means for multiplying the first addition signal and the second addition signal to generate a third multiplication signal; means for adding the first multiplication signal and the second multiplication signal to generate a third addition signal; means for subtracting the third addition signal from the third multiplication signal to generate a subtraction signal; and means for adding a left-shifted version of the first multiplication signal, the second multiplication signal, and a left-shifted version of the subtraction signal.