# US 2021/0240380 A1 · Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory device

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- Number: US 2021/0240380 A1
- Document ID: US20210240380A1
- Status: Published application
- Kind: A1
- Application number: 16/777,812
- Filed: 2020-01-30
- Published: 2021-08-05
- Earliest claimed: 2020-01-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Aliasgar S. Madraswala; Kristopher H. Gaewsky; Siddhanth Munukutla; Tanya Wanchoo; Heonwook Kim
- Web page: https://patentgrep.com/patent/US20210240380A1

## CPC

- G06F 3/0652: {Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0611: {in relation to response time}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2216/18: Flash erasure of all the cells in an array, sector or block simultaneously
- G11C 2216/20: Suspension of programming or erasing cells in an array in order to read other cells in it
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

## Claims

### Claim 1

A memory device, comprising:
a host interface, to receive an erase command from a memory controller coupled with the memory device, to erase at least a portion of data stored in the memory device, wherein the erase command comprises a sequence of erase segments that provide an erase voltage to the memory device, wherein the memory controller is to generate the erase command in response to a request provided by a host coupled with the memory controller, wherein the host is to initiate memory access requests to be executed by the memory device; and
a control circuit coupled with the host interface, to control an execution of the erase command in a memory cell array of the memory device, to erase the portion of data.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the memory device is to grant access to the memory device for servicing at least one of the memory access requests initiated by the host, between at least two adjacent erase segments in the erase sequence.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the memory device is to suspend an erase operation associated with the erase command, and grant access to the memory device at a time corresponding to a completion of a first erase segment of the two adjacent erase segments.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the erase segments in the sequence comprise micro-pulses with the erase voltage.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the sequence includes eight micro-pulses.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein the erase voltage is about 20 V, and wherein a duration of a micro-pulse in the sequence is about 807 microseconds.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the memory device comprises a flash memory.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the memory device is a 3D NAND memory device.

### Claim 9 (depends on 7)

The memory device of claim 7, wherein the memory controller is integrated with a host processor in a system on chip (SoC).

### Claim 10

A computing device, comprising:
a host, to initiate memory access requests;
a memory device, to store data; and
a memory controller coupled with the host and the memory device, wherein the memory controller is to generate an erase command in response a request, provided by the host, to erase at least a portion of the data stored in the memory device, wherein the erase command comprises a sequence of erase segments that provide an erase voltage to the memory device.

### Claim 11 (depends on 10)

The computing device of claim 10, wherein the memory controller is to provide the erase command to the memory device for execution, to erase the requested portion of data.

### Claim 12 (depends on 10)

The computing device of claim 10, wherein the memory controller is to grant access to the memory device for servicing at least one of the memory access requests initiated by the host, between at least two adjacent erase segments in the sequence.

### Claim 13 (depends on 12)

The computing device of claim 12, wherein the memory controller is to suspend an erase operation associated with the erase command, and grant access to the memory device at a time corresponding to a completion of a first erase segment of the two adjacent erase segments.

### Claim 14 (depends on 12)

The computing device of claim 12, wherein the memory device comprises a flash memory.

### Claim 15

A method, comprising:
generating, by a memory apparatus of a computing device, an erase command in response to a request, provided by a host of the computing device, to erase at least a portion of data stored in the memory apparatus, including generating a sequence of erase segments that provide an erase voltage for erasing the at least a portion of data stored in the memory apparatus.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
suspending, by the memory apparatus, an erase operation associated with the erase command; and
granting, by the memory apparatus, access to memory of the memory apparatus at a time corresponding to a completion of a first erase segment of two adjacent erase segments, to service at least one of memory access requests initiated by the host, between the at least two adjacent erase segments in the sequence, wherein the erase segments in the sequence comprise micro-pulses with the erase voltage.

### Claim 17 (depends on 16)

The method of claim 16, further comprising: performing, by the memory apparatus, a verification of the erase operation, to determine that the portion of data stored in the memory apparatus has been erased.

### Claim 18 (depends on 16)

The method of claim 16, further comprising: verifying, by the memory apparatus, that a total number of erase segments in the sequence equals a predetermined value.

### Claim 19 (depends on 18)

The method of claim 18, wherein the memory apparatus comprises a flash memory.

### Claim 20 (depends on 18)

The method of claim 18, wherein the memory apparatus comprises a NAND memory.