# US 2021/0240358 A1 · Storage System and Method for Boundary Wordline Data Retention Handling

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- Number: US 2021/0240358 A1
- Document ID: US20210240358A1
- Status: Published application
- Kind: A1
- Application number: 16/780,281
- Filed: 2020-02-03
- Published: 2021-08-05
- Earliest claimed: 2020-02-03
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Sahil Sharma; Nian Niles Yang; Phil Reusswig; Rohit Sehgal; Piyush A. Dhotre
- Web page: https://patentgrep.com/patent/US20210240358A1

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/0757: {by exceeding a time limit, i.e. time-out, e.g. watchdogs}
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/409: Read-write [R-W] circuits
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/32: Timing circuits
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G06F 2201/81: Threshold
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

## Claims

### Claim 1

A storage system, comprising:
a memory comprising a first single-level cell (SLC) memory area, a second SLC memory area, and a multi-level cell (MLC) memory area; and
a controller configured to communicate with the memory and further configured to:
write data to both the first SLC memory area and the MLC memory area;
determine whether an amount of time that has passed since a last-written wordline in the MLC memory area was written is longer than a threshold amount of time; and
in response to determining that the amount of time is longer than the threshold amount of time:
copy data from a wordline in the first SLC memory area that corresponds to the last-written wordline in the MLC memory area to a wordline in the second SLC memory area; and
update a mapping table to reflect the copy.

### Claim 2 (depends on 1)

The storage system of claim 1, wherein the controller is further configured to, in response to a command to read the MLC memory area:
read data from wordlines prior to the last-written wordline in the MLC memory area; and
instead of reading the last-written wordline in the MLC memory area, read the data from the wordline in the second SLC memory area.

### Claim 3 (depends on 1)

The storage system of claim 1, wherein the controller is further configured to log an identification of the last-written wordline in the MLC memory area and a time when the last-written wordline was written.

### Claim 4 (depends on 3)

The storage system of claim 3, wherein the identification and time are logged in volatile memory in the storage system.

### Claim 5 (depends on 1)

The storage system of claim 1, wherein the controller is further configured to de-commit the data from the first SLC memory area.

### Claim 6 (depends on 1)

The storage system of claim 1, wherein the MLC memory area comprises a quad-level cell (QLC) memory area.

### Claim 7 (depends on 1)

The storage system of claim 1, wherein the memory comprises a three-dimensional memory.

### Claim 8 (depends on 1)

The storage system of claim 1, wherein the storage system is configured to be integrated in a host.

### Claim 9 (depends on 1)

The storage system of claim 1, wherein the storage system is configured to be removably connected with a host.

### Claim 10

In a storage system including a memory comprising a single-level cell (SLC) block and a multi-level cell (MLC) block, a method comprising:
programming data to both the SLC block and the MLC block;
determining whether a predetermined amount of time has passed since a boundary wordline in the MLC block was programmed; and
in response to determining that the predetermined amount of time has passed, re-programming the data in the boundary wordline in the MLC block.

### Claim 11 (depends on 10)

The method of claim 10, wherein the data is programmed in the boundary wordline in the MLC block using a fine programing technique, and wherein the data is re-programmed in the boundary wordline using a double fine programing technique.

### Claim 12 (depends on 10)

The method of claim 10, further comprising logging an identification of the boundary wordline in the MLC block and a time when the boundary wordline was written.

### Claim 13 (depends on 12)

The method of claim 12, wherein the identification and time are logged in volatile memory in the storage system.

### Claim 14 (depends on 10)

The method of claim 10, further comprising de-committing the data from the SLC block.

### Claim 15 (depends on 10)

The method of claim 10, wherein the MLC block comprises a quad-level cell (QLC) block.

### Claim 16

A storage system, comprising:
a memory comprising a single-level cell (SLC) memory area and a second SLC memory area;
means for writing data to both the SLC memory area and the MLC memory area;
means for determining whether a last-written wordline in the MLC memory area has a data retention problem; and
means for, in response to determining that the last-written wordline in the MLC memory area has a data retention problem, correcting the data retention problem.

### Claim 17 (depends on 16)

The storage system of claim 16, wherein the data retention problem is corrected by copying data from a wordline in the SLC memory area that corresponds to the last-written wordline in the MLC memory area to a wordline in another SLC memory area.

### Claim 18 (depends on 16)

The storage system of claim 16, wherein the data retention problem is corrected by re-programming the data in the last-written wordline in the MLC memory area.

### Claim 19 (depends on 18)

The storage system of claim 18, wherein the data is programmed in the last-written wordline in the MLC memory area using a fine programing technique, and wherein the data is re-programmed in the last-written wordline using a double fine programing technique.

### Claim 20 (depends on 16)

The storage system of claim 16, further comprising means for logging an identification of the last-written wordline in the MLC memory area and a time when the last-written wordline was written.